Memory array structure and operating method thereof

Abstract

The invention provides a memory array structure and an operating method thereof. The memory array structure comprises a plurality of serial structures which are arranged in parallel along a first direction and a second direction, a plurality of word lines which are arranged in parallel along the second direction, a first selection line along the second direction, a second selection line along the section direction, and a plurality of parallel bit lines along the first direction, wherein each serial structure comprises a first selection transistor, a plurality of memory units and a second selection transistor which are sequentially connected with one another in series in the first direction, and the storage units are logically equivalent to a mode that one selection tube is serially connected with one or more storage tubes; each word line is connected with a grid of each storage unit; the first selection line is connected with a grid of each first selection transistor; the second selection line is connected with a grid of each second selection transistor; and the drain ends of the first selection transistors of the serial structures are connected with one bit line adjacent to the serial structures, and the source ends of the second selection transistors of the serial structures are connected with another bit line adjacent to the serial structures. According to the memory array structure, the storage density of a memory array can be effectively enhanced.

Description

technical field [0001] The invention relates to the field of memory technology, in particular to a memory array structure and an operation method thereof. Background technique [0002] ROM (read-only memory) is generally used to store programs that do not need to be changed, and is a non-volatile memory. It can only be read out during the working process, unlike random access memory, which can be rewritten quickly and conveniently. For ease of use, PROM (Programmable Read-Only Memory), EPROM (Erasable Programmable Read-Only Memory) and EEPROM (Electrically Erasable Programmable Read-Only Memory) were further developed. Among them, EPROM needs to be erased by ultraviolet light, which is inconvenient and unstable. The EEPROM produced in the 1980s overcomes the shortcomings of EPROM. There are various structures of EEPROM, among which the device using floating gate type non-volatile memory as storage unit can realize faster erasing. [0003] figure 1 Shown is a schematic d...

AI Technical Summary

Problems solved by technology

For the double-bit EEPROM array structure, if the source and drain regions are routed in the active region, the resistance of the route will increase and the operation speed of the array will slow down; if metal routes are used, more contact holes are required in the array , reducing the storage density of the array

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