Node controller, parallel computing server system and routing method

Abstract

The invention discloses a node controller, a parallel computing server system and a route method, wherein the node controller is located in one node of the parallel computing server system and can comprise a high-speed interconnected interface and an external network interface, the high-speed interconnected interface is connected with a high-speed interconnected interface of a processor in the node and used for carrying out mutual data transmission with the high-speed interconnected interface of the processor, and the external network interface is connected with external network interfaces of other nodes in the parallel computing server system and used for carrying out mutual data transmission with the external network interfaces of the other nodes. Therefore, scale of the computing server system can be expanded, and performance of the computing server system is improved.

Description

technical field [0001] The invention relates to the communication field, in particular to a node controller, a parallel computing server system and a routing method. Background technique [0002] The current IT development trend is gradually expanding to the high-end server field, and the demand for big data processing, cloud storage and computing has increased sharply. Such applications have a large demand for system memory space and the number of processors. A parallel computing server system based on Cache coherence Non-Uniform Memory Access (CC-NUMA) architecture can meet such market demands. [0003] Such as figure 1 As shown in FIG. 2 , it is a schematic diagram of the structural composition of a computing server system under the CC-NUMA architecture in the prior art. Such as figure 1 As shown, in the CC-NUMA architecture parallel computing server system, the high-speed interconnection interface between the processors is used to form a computing server system by dir...

AI Technical Summary

Problems solved by technology

[0004] However, because the high-speed interconnection interface of the processor itself is generally composed of multiple sets of high-speed differential signals, and the number of pins is large, the area of ​​the processor chip is larger, so the number of high-speed interconnection interfaces of the general processor is not many, which leads to The scale of the entire computing server system is limited by the number of high-speed interconnection ports of the processors. Generally, only 8 processors are directly connected, which severely limits the system scale;

[0005] In a system where each processor is directly connected, the reliability is poor. If any processor is hot-swapped or the interconnection link is damaged, the system performance will degrade or even crash; too much data passing through a certain processor, Routing is too busy, it will also lead to a sudden drop in system performance

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