A device for executing memory access instructions

Abstract

The invention discloses an execution method for memory access instructions. The method comprises the following steps: the memory access instructions record age information and date included in a writing instruction by a memory access data delivery device in a front end disorder execution phase; and during the execution of a reading instruction, required data relative to the writing instruction services as the data delivered by the reading instruction via the memory access data delivery device. According to the invention, a new mechanism, namely an address identification technology, is provided on the basis of re-execution and filtering of the reading instruction, and speculative quick access to relative detection is achieved via a filter device realizing the re-execution of the reading instruction, and meanwhile, the writing instruction re-executing technology is adopted to achieve memory access of relative violation detection, and the delay of the execution of the reading instruction is reduced via quick speculative memory access data delivery, so as to greatly optimize the execution performance of the reading instruction.

Description

technical field [0001] The invention relates to modern superscalar processor memory access instruction execution technology, in particular to address identification-based memory access instruction execution device and method thereof. Background technique [0002] With the rapid development of integrated circuit manufacturing technology, the performance gap between the processor and the memory is gradually widening, so that the memory access delay, especially the memory access delay of the read instruction, has gradually become the main bottleneck of the performance improvement of modern superscalar processors. . In traditional superscalar processors, read instructions completed by data forwarding between memory access instructions account for only 15% of all read instructions, and other read instructions must be obtained by accessing the data cache at the first level or lower. required data. The access time of these data caches exceeds one processor clock cycle, and the ac...

AI Technical Summary

Problems solved by technology

The access time of these data caches exceeds one processor clock cycle, and the access time of these high-speed data caches will increase further as the ratio of wire delay to the overall circuit delay continues to increase.

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