Reset method of internal memory of chip based on scan chain

Abstract

The invention discloses a reset method of an internal memory of a chip based on a scan chain. The reset method comprises the implementation steps of: 1) constructing at least one scan chain for a register chain in the chip design stage, and determining the connection relation between a register and a previous register in the scan chain according to a reset value of the register; and 2) in the chip using stage, enabling scan enable signals of every register in the chip to be effective, providing a reset clock, controlling every scan chain to enter a reset scanning state, inputting the reset value of the register of a chain tag of the scan chain into the chain tag of the scan chain, orderly resetting the next register in the scan chain by each register of the scan chain under the control of the reset clock according to the connection relation between the register and the next register in the scan chain, and exiting the reset scanning state after the register at the tail of the scan chain is reset. According to the invention, a reset tree structure required by the conventional synchronous reset method or the conventional asynchronous reset method, and the reset method has the advantages of simplicity in realization and small performance cost.

Description

technical field [0001] The invention relates to the field of digital integrated circuits, in particular to a method for resetting internal registers of chips based on scan chains. Background technique [0002] In a digital integrated circuit, a certain method needs to be used to reset the register so that it has a definite initial state (0 or 1), so as to ensure that the digital integrated circuit can work normally. Common register reset methods include synchronous reset and asynchronous reset. In the synchronous reset structure, when the reset signal is valid, the register is not reset immediately, but the register is reset to a fixed initial value when the clock of the register jumps effectively. In the synchronous reset structure, the reset signal is used as a data signal to participate in the combinational logic operation of the register data input, which increases the combinational logic stages between the registers and has a certain impact on the performance of the di...

AI Technical Summary

Problems solved by technology

This not only consumes a lot of hardware resources, but also brings a certain power consumption overhead of the reset tree, and with the continuous expansion of the scale of digital integrated circuits, the reset tree will continue to increase the complexity of the physical design of the chip, causing great damage to the design and implementation of the chip. Difficulties

[0003] In summary, the existing synchronous reset structure of digital integrated circuits has a certain impact on the performance of the chip

while the asynchronous reset structure has potential stability issues

And whether it is a synchronous reset structure or an asynchronous reset structure, it is necessary to design and implement a global reset tree structure, which not only brings additional power consumption overhead, but also brings great difficulties to the physical implementation of the chip.

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