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Conversion method of virtual and real addresses of many-core processor

A technology of many-core processors and virtual and real addresses, applied in the computer field, can solve the problems of inapplicability to many-core processors, affecting the performance of the processor system, large overhead, etc., to achieve the effect of small overhead, low overhead, and reduced overhead

Active Publication Date: 2013-02-13
JIANGNAN INST OF COMPUTING TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] However, the virtual-to-real address translation according to the prior art is either not suitable for many-core processors, or will bring huge overhead
In addition, the deficiencies of the existing technology also include TLB+ page table technology, segment table technology and segment page table technology of general-purpose processors, etc.
Moreover, shared Cache (high-speed cache) is generally an important factor for improving the performance of processor systems, but in many-core systems, due to the competition of many cores, access to shared Cache sometimes affects the performance of processor systems

Method used

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  • Conversion method of virtual and real addresses of many-core processor
  • Conversion method of virtual and real addresses of many-core processor
  • Conversion method of virtual and real addresses of many-core processor

Examples

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no. 1 example

[0035] figure 1 A flow chart of a virtual-to-real address translation method for a many-core processor according to the first embodiment of the present invention is schematically shown. Such as figure 1 As shown, the many-core processor virtual-to-real address conversion method according to the first embodiment of the present invention includes the following steps:

[0036] The first step S1: the request arbitrator arbitrates the instruction flow requests and data flow requests from each processor core; wherein, preferably, the request arbitrator can be divided into multiple stages according to the core scale of the many-core processor.

[0037] Second step S2: Centrally replace the arbitrated instruction flow and data flow requests through the instruction flow substitution table and the data flow substitution table; wherein, each processor core is fixed in the instruction flow and data flow substitution table Allocate a number of entries, and among them, after the instructi...

no. 2 example

[0049] figure 2 A flow chart of a virtual-to-real address conversion method for a many-core processor according to the second embodiment of the present invention is schematically shown. Such as figure 2 As shown, the many-core processor virtual-real address translation method according to the second embodiment of the present invention includes the following steps:

[0050] The first step S1: the request arbitrator arbitrates the instruction flow requests and data flow requests from each processor core; wherein, preferably, the request arbitrator can be divided into multiple stages according to the core scale of the many-core processor.

[0051] The second step S20: perform the instruction stream substitution of the processor core through the instruction stream substitution table; wherein, each processor core fixedly allocates an entry in the instruction stream substitution table (such as image 3 shown), where, in the instruction stream substitution table and the data stre...

no. 3 example

[0053] The second embodiment above corresponds to the case where each processor core permanently allocates one entry in the instruction stream substitution table, and correspondingly, for the case where each processor core permanently allocates multiple entries in the instruction stream substitution table, Figure 4 A flow chart of a virtual-to-real address conversion method for a many-core processor according to the third embodiment of the present invention is schematically shown. Such as Figure 4 As shown, the many-core processor virtual-to-real address conversion method according to the third embodiment of the present invention includes the following steps:

[0054] The first step S1: the request arbitrator arbitrates the instruction flow requests and data flow requests from each processor core; wherein, preferably, the request arbitrator can be divided into multiple stages according to the core scale of the many-core processor.

[0055] The second step S20: perform the i...

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Abstract

A conversion method of virtual and real addresses of a many-core processor comprises the following steps: step one, requesting an arbiter to arbitrate an instruction stream request and a data stream request from various processor cores; and step two, carrying out centralized substitution on an arbitrated instruction stream and an arbitrated data stream through an instruction stream substitution list and a data stream substitution list, wherein each processor core is fixedly distributed into a plurality of items in the instruction stream substitution list and the data stream substitution list, and after the instruction stream of the core is subjected to the unauthorized and bound check, and the substitution list item corresponding to the core is indexed by the virtual address, the physical address is substituted by a configurable substitution algorithm method, and the substitution list item comprises information on Cache consistency attribute configuration. The information on the Cache consistency attribute configuration comprises whether the arbitrated instruction stream and the arbitrated data stream can be cached to access, whether the cached strategy is subjected to direct writing or write-back, and whether the Cache access is subjected to write allocate.

Description

technical field [0001] The present invention relates to the field of computer technology, and more specifically, the present invention relates to a method for converting virtual and real addresses of many-core processors. Background technique [0002] With the improvement of single-core processor chip integration and main frequency, processor technology has encountered problems such as manufacturing cost, power consumption, heat dissipation, etc., prompting multi-core and multi-thread technology to become a new direction for the development of processor systems. A processor system integrating hundreds or even thousands of cores is generally called a many-core processor system. The increase in the number of cores in multi-core processor systems and many-core processor systems ensures continuous improvement in computing and data processing capabilities. [0003] A processor system integrating hundreds or even thousands of cores is generally called a many-core processor system...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38
Inventor 郑方李宏亮许勇任秀江高红光唐勇杨萱
Owner JIANGNAN INST OF COMPUTING TECH
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