Phase change memory array blocks with alternate selection

Abstract

A phase change memory is disclosed. The phase change memory has a plurality of block units. The block units are alternately selected. The alternate block unit selection suppresses peak current ground bouncing on sub-wordline and connected ground line through sub-wordline driver transistor. An alternate bitline selection avoids adjacent cell heating interference in the selected block unit.

Description

[0001] related application [0002] This application claims the benefit of US Provisional Patent Application No. 61 / 328,421, filed April 27, 2010, which is hereby incorporated by reference in its entirety. technical field [0003] The present invention generally relates to semiconductor memories. More specifically, the present invention relates to phase change memory. Background technique [0004] At least one type of phase-change memory device—PRAM (Phase Change Random Access Memory)—uses an amorphous state to represent a logic "1" and a crystalline state to represent a logic "0." In a PRAM device, the crystalline state is called the "set state" and the amorphous state is called the "reset state". Thus, a memory cell in a PRAM stores a logic "0" by setting the phase change material in the memory cell to a crystalline state, and the memory cell stores a logic "1" by setting the phase change material in the memory cell to an amorphous state. [0005] The phase change mater...

AI Technical Summary

Problems solved by technology

As the voltage level of the word line increases, the programming characteristics of the plurality of memory cells deteriorate

For example, in a Figure 1B In a diode-type phase-change memory cell of a diode, if the voltage level of the word line W / L increases undesirably, the diode 22 may not be fully turned on

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