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Internal clock gating apparatus

An internal clock, clock technology, used in digital data processing components, instruments, electrical digital data processing, etc.

Active Publication Date: 2012-11-28
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Also, longer latency times may prevent the core processor unit from achieving high performance by further increasing its operating frequency

Method used

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Embodiment Construction

[0038] The making and using of preferred embodiments of the invention are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

[0039] The invention will be described in the context of a preferred embodiment, the internal clock gating means comprising a domino logic clock and a static logic clock. However, the present invention can also be applied to various clock gating circuits.

[0040] Initially, referring to figure 1 , shows a block diagram of an internal clock gating device according to an embodiment. The internal clock gating device 100 includes: a static logic module 102 and a domino logic module 104 . The domino logic block 104 includes: a first input connected to the clock s...

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Abstract

An internal clock gating apparatus comprises a static logic block and a domino logic block. The static logic block is configured to receive a clock signal and a clock enable signal. The domino logic block is configured to receive the clock signal and a control signal from an output of the static logic block. The static logic block and the domino logic block are further configured such that an output of the domino logic block generates a signal similar to the clock signal in phase when the clock enable signal has a logic high state. On the other hand, the output of the domino logic block generates a logic low signal when the clock enable signal has a logic low state. Furthermore, the static logic block and the domino logic block can reduce the setup time and delay time of the internal clock gating apparatus respectively.

Description

technical field [0001] The invention relates to the field of integrated circuits, and more specifically, to an internal clock gating device. Background technique [0002] Various battery powered portable devices such as mobile phones, notebook computers, etc. have become popular. Each portable device may utilize multiple integrated circuits. To extend the battery life of portable devices, the power consumption of integrated circuits becomes a concern. Various energy saving methods have been adopted, thereby improving the power consumption of portable devices. Among these methods, reducing clock network power consumption is an effective method, thereby reducing the overall power consumption of modern portable devices including several high-performance digital systems. [0003] Digital systems may include various synchronization circuits that require a clock to synchronize all components. When the semiconductor technology is further developed, the frequency of the clock si...

Claims

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Application Information

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IPC IPC(8): G06F1/04
CPCG06F1/3237G06F1/04G06F1/3287Y02D10/00
Inventor 刘祈麟邹宗成林洋绪陆晓文
Owner TAIWAN SEMICON MFG CO LTD
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