Method for high-speed writing operation of dynamic random access memory (DRAM)

Abstract

The invention relates to the technical field of memories and particularly relates to a method for high-speed writing operation of a dynamic random access memory (DRAM). According to the method, a DRAM cell adopting a logical process is of a 2T gain cell structure and comprises a write-in tube Qw and a readout tube Qr, and an active area capacitor of the write-in tube Qw and a gate capacitor of the readout tube Qr constitute the storage capacitor of the cell. According to the method, in a writing circuit, a domino logic part is a drive circuit which executes the write-in operation of the cell, and evaluation tube sets M1-M4 of the domino logic part receive a cell read-out small signal and an outside write-in signal which are amplified by a sense amplifier respectively. When a writing drive enable signal (WPCH) is opened, the level of a domino logic prenode changes according to whether the evaluation tube sets M1-M4 are connected or not to enable the level of a wideband laser (WBL) of an output terminal of an inverter (INV) to swing, so that the write-in to the cell is completed. According to the method disclosed by the invention, the technical problems that as a non-logic process is adopted to produce capacitors of the traditional 1T1C DRAM, the application of the DRAM in embedded equipment is difficult, and the like can be solved.

Description

technical field [0001] The invention relates to the technical field of memory, in particular to a high-speed write operation method of a dynamic random access memory. Background technique [0002] DRAM write operations follow the principle of read-write-back. Traditional DRAM write operations and related circuits such as figure 1 As shown, there are two improvements: as figure 1 (a) When a write operation occurs, the write-back step for the accessed unit and its adjacent units depends on the drive of the sense amplifier (SA), so that as the array capacity increases, the number of bit line units increases, and the write-back operation When the load on the sense amplifier is large, the writing time of the cell becomes longer. In addition, if figure 1 (b) The input end of the writing circuit shown in (b) is the column gate tube Mn / Mn-1 composed of transmission tubes. This structure makes the strong signal from the outside can only pass through the column after the sense ampl...

AI Technical Summary

Problems solved by technology

[0003] The main purpose of the present invention is to solve the traditional 1T1C dynamic random access memory (DRAM) unit due to the shortcomings of non-logic technology for making capacitors, which makes the application of DRAM in embedded devices difficult and other technical problems, and provides a dynamic random access memory high-speed write operation method

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