Novel static random access memory (SRAM) storage unit preventing single particle from turning

Abstract

The invention discloses a novel static random access memory (SRAM) storage unit preventing a single particle from turning. The storage unit comprises a first input / output port, a first potential turning recovery driving circuit, a voltage retaining circuit, a second potential turning recovery driving circuit and a second input / output port which are connected in series with one another sequentially. An automatic recovery function for voltage turning when a sensitive node is impacted by a high-energy particle can be realized; according to a simulation result of a TSMC 0.18 mu_m process, a turning threshold value LETth is more than 500 MeV / (mg.cm<2>); compared with the conventional storage unit preventing the single particle from turning, the SRAM storage unit has the characteristic of high writing speed; the recovery time can be effectively shortened; by adopting a unidirectional clock and a small-clock amplitude, a clock network is relatively simple and relatively high in reliability; the clock is only connected with the gate of a read-write transistor, and the clock load is relatively small; and the sensitive node can be used for reinforcing multi-node turning of the single particle, which is caused by drains positioned on a P-type tube and an N-type tube..

Description

Technical field: [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a novel anti-single event reversal SRAM storage unit. Background technique: [0002] As the critical dimensions of integrated circuits continue to decrease with the continuous development of process technology, the critical charge of nodes will also decrease, so the soft errors caused by single event effects will be more significant. In order to ensure the reliability of spacecraft in the space radiation environment, anti-radiation hardening measures must be taken for integrated circuits. High-performance memory cells have the characteristics of large critical charge, fast read and write speed, short flip recovery time, and low power consumption. WHIT published (S.Whitaker, J.Canaris and K.Liu, "SEU Hardened Memory Cells for a CCSDS Reed Solomon Encoder," IEEE Transactions on Nuclear Science, vol.38, No.6, pp.1471-1477, Dec. 1991.) The anti-single event...

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WHIT published (S.Whitaker, J.Canaris and K.Liu, "SEU Hardened Memory Cells for a CCSDS Reed Solomon Encoder," IEEE Transactions on Nuclear Science, vol.38, No.6, pp.1471-1477, Dec. 1991.) The anti-single event flipping memory unit mentioned in has good single event flipping stability, but due to the potential degradation phenomenon, the transistor cannot be completely turned off, and the static power consumption is very large

LIU mentioned an improved type in (Liu M N; Whitaker S "Low power SEU immune CMOS memory circuits", IEE Transactions on Nuclear Science, Vol.39, no 6, pp.1679-1684, December.1992.) The anti-single event flip memory unit effectively reduces static power consumption, but the flip recovery time is relatively long and affects the operating frequency

HIT in (Velazco R; Bessot D, "Two CMOS memorycells suitable for the design of SEU-tolerant VLSI circuits", IEEE IEE Transactions on Nuclear Science, Vol.41, No.6, December.1994.) mentioned in the new anti- The single event flip memory unit is characterized by superior performance, but with a large clock load

Mentioned in ZHANG (Guohe Zhang, Jun Shao, Feng Liang and Dongxuan Bao, "A novel single event upset hardened CMOS SRAM cell," IEICE Electronics Express, Vol.9, No, 3, 140-145, 2012.) Memory cell, which has the advantage of short flip recovery time, but longer write time

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