Array substrate and manufacturing method thereof

Abstract

The embodiment of the invention provides an array substrate and a manufacturing method thereof, which relate to the field of manufacturing of display elements and are used for reducing induced voltage of pixel electrodes to reduce screen flicker. The array substrate comprises a transparent substrate; grid lines and data lines crossed horizontally and longitudinally are arranged on the transparent substrate, and thin film transistors and the pixel electrodes are arranged in pixel units defined by the grid lines and the data lines; and grid electrodes of the thin film transistors are connected with the grid lines, source electrodes of the thin film transistors are connected with the data lines, and leakage electrodes of the thin film transistors are connected with the pixel electrodes. The array substrate is characterized in that the grid electrodes of the thin film transistors in an area just opposite to the leakage electrodes are thicker than that of the grid electrodes in an area just opposite to channels of the thin film transistors. The array substrate and the manufacturing method thereof are used in the field of manufacturing of the display elements.

Description

technical field [0001] The invention relates to the field of display manufacturing, in particular to an array substrate and a manufacturing method thereof. Background technique [0002] refer to figure 1 The top view of the array substrate shown and figure 2 As shown in the cross-sectional view of the A-A direction, the structure of the array substrate 10 in the prior art is: on the transparent substrate 109, gate lines and data lines intersecting horizontally and vertically are formed, and pixels defined by the gate lines and data lines A thin film transistor 104 and a pixel electrode 103 are arranged in the unit; wherein the thin film transistor 104 includes: a gate 105 , a source 106 and a drain 107 , and the drain 107 is electrically connected to the pixel electrode 103 through a via hole. From a top view, it can be seen that the gate 105 and the drain 107 have an overlapping area, which will generate a parasitic capacitance C gd . Due to the C of the drain 107 and ...

AI Technical Summary

Problems solved by technology

[0005] The appearance of the induced voltage will cause the asymmetry of the driving voltage, resulting in the fluctuation of the light transmittance, causing low-frequency brightness changes and head shaking, that is, flickering

In order to reduce the influence of the induced voltage, a larger storage capacitor C is usually used st , but conventionally increases the storage capacitor C st The method, such as increasing the area of ​​the storage capacitor, will lead to a decrease in the aperture ratio

In addition, although it can be seen from the above formula that reducing the parasitic capacitance can also reduce the induced voltage, the design of reducing the parasitic capacitance by changing the overlapping area is difficult to realize due to the strict requirements on the specifications of thin-film transistors in the prior art

Images