Method for extracting and calculating capacitance parameter based on random walk in integrated circuit design

Abstract

The invention relates to a method for extracting and calculating a capacitance parameter based on a random walk in an integrated circuit design, belonging to the technical field of integrated circuit computer aided designs, and comprising the following steps of: (1) setting the combination of the upper and lower dielectric constants of each interface in an integrated circuit and setting up a cubic transition area model, obtaining the relationship between the potential of an area surface grid and a central potential by a numerical way and taking the relationship as an initial transition probability intensity vector, and converting the initial transition probability intensity vector into a transition intensity vector and a corresponding weight numerical vector according to an importance collecting idea, and then processing and storing the transition intensity vector and the corresponding weight numerical vector into a database; and (2) correspondingly modifying a weight sampling way and a weight numerical value in a random walk algorithm by the data calculated in Step (1), and extracting and calculating the capacitance parameter in the integrated circuit. The random walk sampling weight numerical value generated by the method is unified, and the sampling probability tends to a location contributing great to the Gauss surface integral. The method for extracting and calculating the capacitance parameter has higher calculating efficiency and the design period for the integrated circuit is shortened.

Description

technical field [0001] The invention relates to a method for extracting and calculating capacitance parameters based on random walk in integrated circuit design, and belongs to the technical field of integrated circuit computer aided design. Background technique [0002] In the design process of an integrated circuit, a functional description must first be proposed, and then a layout describing the size and structure of the semiconductor process is obtained through logic design and layout design. At this time, "layout verification" is required, that is, to verify whether the above-mentioned design can meet the originally set requirements through computer software simulation. If the requirements are met, the next step of production and manufacturing can be carried out; otherwise, it is necessary to return to logic design and make necessary corrections. This iterative process is repeated until layout verification shows that the design does meet the requirements. In layout ve...

AI Technical Summary

Problems solved by technology

Among them, a method is proposed to pre-calculate the data information required in the random walk algorithm under the condition of a given integrated circuit process, such as adding the transition probability distribution of the transfer area of ​​the two dielectric layers, and the corresponding weight distribution data, and apply it to the random walk In the algorithm, it solves the problem of slow calculation rate or large memory consumption of the current similar algorithms in the case of multi-layer media

Through observation, it is found that this algorithm and other similar algorithms do not further optimize the weights and sampling methods used in the Monte Carlo process involved in the random walk algorithm, resulting in low algorithm efficiency.

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