Generation and verification method of test vector

A technology of test vectors and verification methods, which is applied in the field of generation and verification of functional test vectors, can solve problems such as low work efficiency, large workload, and different numbers of signal names, and achieve the effect of improving production efficiency

Active Publication Date: 2012-07-11
西安翔腾微电子科技有限公司
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Problems solved by technology

Although scripts such as perl can be used to process, but for different projects, the number of signal names is different, the ATE and test environment used are different, the versatility of the script is poor, and there is still a large workload
Except for the ...

Method used

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  • Generation and verification method of test vector
  • Generation and verification method of test vector
  • Generation and verification method of test vector

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Embodiment Construction

[0029] see figure 1 , the method for generating test vectors of the present invention, its preferred embodiment is realized by the following steps:

[0030] Step 1: Create a hardware description language HDL file and define a file variable for recording test vectors; the hardware description language HDL file contains a test vector generation module with or without input and output signals; the name of the module can be named "vector_gen_tb " can also be any other identifier that meets the grammatical requirements;

[0031] Step 2: Define a corresponding signal for each input and output signal of the entity to be tested in the module of step 1), which is used to monitor the input and output values ​​of the entity to be tested; when necessary, an initial value can also be given;

[0032] Step 3: When the input and output signals of the DUT to be tested are reversed, assign the corresponding signals in step 2) to The legal vector representation value of the corresponding test ...

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Abstract

The invention relates to a generation and verification method of a test vector. A simulation environment is established by utilizing hardware description language, the changes of signals to be recorded can directly recorded into a designated file according to the requirements of vector format of an automatic test device during the simulation, corresponding input excitation can be added to a hardware model by reading back the contents of the file, output is compared to realize verification on a recorded test vector, the test vector required by ATE (automatic test equipment) is directly generated during the simulation and verified by simulation, and manual processing is not required, therefore, the whole process is simplified, the production efficiency is improved and the generation and verification method can be used for testing a digital integrated circuit.

Description

technical field [0001] The invention belongs to the field of integrated circuit testing, and in particular relates to the generation and verification of functional test vectors for testability design. Background technique [0002] At present, usually for integrated circuit testing, functional test vectors need to be provided when performing functional testing on ATE. The existing technology is to use the VCD file generated during functional simulation, perform format conversion and manual processing through certain tools, and generate the VCD files for ATE. required test vectors. Since the VCD file is based on event recording, any flip of the signal during the simulation process will be recorded in the VCD file, so some glitches during the simulation process will also be recorded. However, ATE is limited by the length of the test cycle, and these glitches are not allowed in the test vector. These burrs need to be removed through manual processing of VCD files, which is slo...

Claims

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Application Information

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IPC IPC(8): G01R31/3183
Inventor 田泽郭蒙张荣华赵强蔡叶芳
Owner 西安翔腾微电子科技有限公司
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