Method for forming silicon on insulator-SiGe heterojunction 1T-DRAM (1T-Dynamic Random Access Memory) structure on insulator and formed structure

Abstract

The invention provides a method for forming a SiC-SiGe heterojunction 1T-DRAM (1T-Dynamic Random Access Memory) structure on an insulator. The 1T-DRAM structure formed with the method comprises a semiconductor substrate, an oxygen burying layer and a P type silicon layer, wherein the oxygen burying layer is covered on the semiconductor substrate; the P type silicon layer is covered on the oxygen burying layer, and is provided with an NMOS (N-channel metal oxide semiconductor) device isolated through STI (Shallow Trench Isolation); a channel in the NMOS device is P type SiGe; a source region in the NMOS device is N<+>-SiC; and a drain region in the NMOS device is N<+>-SiGe. Compared with the prior art, the method has the advantages that: a 1T-DRAM unit based on a P-SiGe body region, the N<+>-SiC source region and the N<+>-SiGe drain region is formed, so that a working voltage can be effectively lowered; and meanwhile, an output current difference between reading ''0'' and reading ''1'' is increased simultaneously, so that a signal margin can be increased.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for forming a silicon-carbon-germanium-silicon heterojunction 1T-DRAM structure on an insulator and a structure formed by the method. Background technique [0002] With the continuous shrinking of the feature size of semiconductor integrated circuit devices, in order to obtain sufficient storage capacitance (generally 30fF / cell) for traditional 1T / 1C embedded DRAM units, the capacitor preparation process (stack capacitor or deep trench capacitor) will It is becoming more and more complex, and the process compatibility with logic devices is getting worse and worse. Therefore, Capacitorless DRAM with good compatibility with logic devices will have a good development prospect in the field of high-performance embedded DRAM in VLSI. Among them, 1T-DRAM (One Transistor Dynamic Random Access Memory) has only 4F due to its unit size 2 It has become a research hotspot of...

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Problems solved by technology

[0003] 1T-DRAM is generally a SOI floating body (floating body) transistor. When charging its body region, that is, the accumulation of holes in the body region to complete writing "1", at this time, the substrate effect is caused by the accumulation of holes in the body region, resulting in the transistor's Threshold voltage reduction

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