Carbon silicon-germanium silicon heterojunction 1T-DRAM (Single Transistor Dynamic Random Access Memory) structure on insulator and forming method thereof

Abstract

The invention provides a carbon silicon-germanium silicon heterojunction 1T-DRAM (Single Transistor Dynamic Random Access Memory) structure on an insulator, which comprises a semiconductor base plate, a buried oxide layer and a P-type silicon layer. The buried oxide layer covers the semiconductor base plate, the P-type silicon layer covers the buried oxide layer, and NMOS (N-channel Metal Oxide Semiconductor) devices separated by STI (Shallow Trench Isolation) are arranged on the P-type silicon layer, wherein channels of the NMOS devices are made of P-type germanium silicon. Compared with the prior art, the forming method disclosed by the invention can be applied to formation of the 1T-DRAM unit based on P-SiGe region+N+-SiCS / D, thus the working voltage can be effectively reduced; and simultaneously, output current balance between 0-reading and 1-reading is also increased, i.e. signal margin can be increased.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a silicon-carbon-germanium-silicon-on-insulator heterojunction 1T-DRAM structure and a method for forming the structure. Background technique [0002] With the continuous shrinking of the feature size of semiconductor integrated circuit devices, in order to obtain sufficient storage capacitance (generally 30fF / cell) for traditional 1T / 1C embedded DRAM units, the capacitor preparation process (stack capacitor or deep trench capacitor) will It is becoming more and more complex, and the process compatibility with logic devices is getting worse and worse. Therefore, Capacitorless DRAM with good compatibility with logic devices will have a good development prospect in the field of high-performance embedded DRAM in VLSI. Among them, 1T-DRAM (One Transistor Dynamic Random Access Memory) has only 4F due to its unit size 2 It has become a research hotspot of non-capacitive DRAM a...

AI Technical Summary

Problems solved by technology

However, the main problem of 1T-DRAM based on SOI structure is that the body potential is limited by the hole barrier between the acceptor region and the source and drain. Due to the limited band gap of conventional silicon semiconductors, the change of body potential is limited, and the change of threshold voltage is relatively small. Small (generally only about 0.3V), which makes the readout signal current smaller

However, the improvement of the hole barrier is limited, and the signal current and retention time are not greatly improved.

Images