Electrostatic discharge protection circuit

Abstract

An electrostatic discharge (ESD) protection structure comprises a high voltage P type implanted region disposed underneath an N+ region. The high voltage P type implanted region and the N+ region form a reverse diode or a Zener diode depending on different doping densities. The ESD protection structure further comprises a plurality of P+ and N+ regions. The high voltage P type implanted region and the P+ and N+ regions form a semiconductor device having a breakdown characteristic. In one embodiment, the semiconductor device may be a bipolar PNP transistor. The bipolar PNP transistor and a Zener diode in series connection form an ESD protection circuit. In another embodiment, the semiconductor device may be a Silicon-Controlled Rectifier (SCR), which is series-connected with a reverse diode. Both embodiments provide a reliable ESD protection.

Description

technical field [0001] The present invention relates to the field of circuits, and more specifically, to an electrostatic discharge protection circuit. Background technique [0002] Electrostatic discharge (ESD) is a rapid electrical discharge that flows between two objects due to the build-up of electrostatic charge. Because of the relatively large currents generated by this rapid discharge, ESD can burn out semiconductor devices. In order to reduce semiconductor damage caused by ESD, ESD protection circuits have been developed to provide current discharge paths. When an ESD event occurs, the discharge current is conducted through the discharge path instead of passing through the protected internal circuit. [0003] In semiconductor technology, NMOS transistors, silicon controlled rectifiers (SCRs) and RC-triggered PMOS transistors are widely used. However, with the development of submicron semiconductor technology, the existing ESD protection schemes can no longer meet ...

AI Technical Summary

Problems solved by technology

However, with the development of submicron semiconductor technology, the existing ESD protection schemes can no longer meet the growing needs of the semiconductor industry

For example, in high-voltage applications, SCR or NMOS-based ESD protection circuits can cause latch failure due to insufficient holding voltage

On the other hand, even with a relatively high hold voltage, an RC-triggered PMOS transistor takes up a large chip area

Images