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Manufacturing process of removing metal layer redundancy metal filling

A redundant metal, manufacturing process technology, used in semiconductor/solid-state device manufacturing, electrical components, circuits, etc.

Active Publication Date: 2014-02-05
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Redundant metal improves the uniformity of pattern density, but inevitably introduces additional coupling capacitance between metals

Method used

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  • Manufacturing process of removing metal layer redundancy metal filling
  • Manufacturing process of removing metal layer redundancy metal filling
  • Manufacturing process of removing metal layer redundancy metal filling

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Embodiment Construction

[0041] In order to further explain the technical means and effects of the present invention to achieve the intended purpose of the invention, the manufacturing process for removing redundant metal filling in the metal layer according to the present invention will be described in detail below in conjunction with the accompanying drawings and preferred embodiments.

[0042] Different embodiments of the present invention will be described in detail below to implement different technical features of the present invention. It should be understood that the units and configurations of the specific embodiments described below are used to simplify the present invention, which are only examples and not limiting scope of the invention.

[0043] The present invention proposes a manufacturing process for removing redundant metal filling of metal layers, the process steps of which are as follows:

[0044] 1) Depositing a low-k dielectric layer;

[0045] 2) forming an etch barrier layer on ...

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Abstract

The invention provides a manufacturing process of removing a metal layer redundancy metal filling. The process has the following steps: 1) depositing a dielectric layer with a low k value; 2) forming an etching barrier layer on the deposited dielectric layer with the low k value; 3) completing photolithography and etching so as to remove the etching barrier layer in a non-redundant metal area; 4) depositing again the low k value medium so as to reach low-k-value dielectric layer with a required thickness; 5) completing the photolithography and the etching so as to form a through hole; 6) performing again the photolithography and the etching so as to form a metallic channel and a redundancy metal trough; 7) carrying out filling of lead metal, through hole metal and redundancy metal and completing metal layer deposition; 8) carrying out chemical mechanical planarization to the metal layer; 9) continuously carrying out chemical mechanical planarization to the low-k-value dielectric layer and a metal mixing layer and further removing the redundancy metal. In the invention, through a technology of further removing the redundancy metal by using the chemical mechanical planarization during making single damascene and dual damascene interconnection, coupling capacitance in and between the metal layers caused by the redundancy metal filling can be effectively reduced or eliminated. The process is suitable for practical usage.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a manufacturing process for removing redundant metal filling in a metal layer. Background technique [0002] As the integration level of semiconductor chips continues to increase, the feature size of transistors continues to shrink. After entering the 130nm technology node, limited by the high resistance characteristics of aluminum, copper interconnection gradually replaces aluminum interconnection and becomes the mainstream of metal interconnection. Since the copper dry etching process is not easy to realize, the manufacturing method of the copper wire cannot be obtained by etching the metal layer like the aluminum wire. The widely used manufacturing method of copper wire is damascene technology called damascene process. In this process, a low-k dielectric layer is first deposited on the silicon wafer, and then a metal wire groove is formed in the dielectric layer by ph...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768
Inventor 毛智彪胡友存戴韫青王剑
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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