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Manufacturing process for removing redundant filled metal from metal layers

A redundant metal and manufacturing process technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., to achieve the effect of eliminating coupling capacitance

Active Publication Date: 2014-02-05
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Redundant metal improves the uniformity of pattern density, but inevitably introduces additional coupling capacitance between metals

Method used

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  • Manufacturing process for removing redundant filled metal from metal layers
  • Manufacturing process for removing redundant filled metal from metal layers
  • Manufacturing process for removing redundant filled metal from metal layers

Examples

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Embodiment Construction

[0033] In order to further explain the technical means and effects of the present invention to achieve the intended purpose of the invention, the manufacturing process for removing redundant metal filling in the metal layer according to the present invention will be described in detail below in conjunction with the accompanying drawings and preferred embodiments.

[0034] Different embodiments of the present invention will be described in detail below to implement different technical features of the present invention. It should be understood that the units and configurations of the specific embodiments described below are used to simplify the present invention, which are only examples and not limiting scope of the invention.

[0035] The present invention proposes a manufacturing process for removing redundant metal filling of metal layers, the process steps of which are as follows:

[0036] 1) Depositing a low-k dielectric layer;

[0037] 2) forming an etch barrier layer on ...

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Abstract

The invention provides a manufacturing process for removing redundant filled metal from metal layers, wherein the process comprises the following steps of: 1) depositing a low-k-value medium layer; 2) forming an etching blocking layer on the deposited low-k-value medium layer; 3) completing photoetching and etching to remove an etching blocking layer at the non-redundant metal region; 4) depositing the low-k-value medium layer again to obtain the low-k-value medium layer with the required thickness; 5) carrying out photoetching and etching again to form a metal conducting wire groove and a redundant metal groove; 6) filling the conducting wire metal and the redundant metal, and completing the deposition of the metal layers; 7) carrying out chemical and mechanical grinding on the metal layers; and 8) carrying out chemical and mechanical grinding continuously on the low-k-value medium layer and a metal mixed layer, and further removing the redundant metal. According to the method, through the process that the redundant metal is further removed by utilizing chemical and mechanical grinding in manufacturing single Damascus and double Damascus metal interconnection, the coupling capacitance in the metal layers and between the metal layers caused by redundant filed metal can be reduced or eliminated effectively, and the manufacturing process is very practical.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a manufacturing process for removing redundant metal filling in a metal layer. Background technique [0002] As the integration level of semiconductor chips continues to increase, the feature size of transistors continues to shrink. After entering the 130nm technology node, limited by the high resistance characteristics of aluminum, copper interconnection gradually replaces aluminum interconnection and becomes the mainstream of metal interconnection. Since the copper dry etching process is not easy to realize, the manufacturing method of the copper wire cannot be obtained by etching the metal layer like the aluminum wire. The widely used manufacturing method of copper wire is damascene technology called damascene process. In this process, a low-k dielectric layer is first deposited on the silicon wafer, and then a metal wire groove is formed in the dielectric layer by ph...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768
Inventor 毛智彪胡友存戴韫青王剑
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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