Real-time conversion transmission method and device of parallel-series data stream for cross asynchronous clock domain

Abstract

The invention discloses a real-time conversion transmission method and device of parallel-series data stream for cross asynchronous clock domain, comprising a parallel data synchronizer, which is used for capturing the data stream periodically in real time and storing into the parallel data synchronizer under the control of a serial clock CLKS which is synchronous to output device of serial data and an enabling controlling signal CS sent out by serial timing controller which is synchronous to clock CLKP; the serial timing controller, monitoring clock CLKP periodically in the clock domain of clock CLKS, distinguishing indeterminate state of clock CLKP, the indeterminate state being a time domain zone of a data transmission zone; when distinguishing that the capturing moment is in a time zone of the data transmission zone of clock CLKP, the serial timing controller cyclically adjusts capturing moment until the capturing moment is in the time zone of determined state of clock CLKP, the determined state being the time zone besides the data transmission zone; the output device of serial data, reading the data stream of parallel data synchronizer and output serially under the control of the serial timing controller. The invention is characterized by being simple and reliable, good practicability and being in favor of applying in the large scale integrated circuit.

Description

technical field [0001] The invention relates to the technical field of conversion circuits, in particular to a method and device for real-time conversion and transmission of parallel and serial data streams across an asynchronous clock domain. Background technique [0002] Parallel-to-serial conversion circuit is a common data processing circuit that people have studied for a long time, but in some designs people only consider that the input parallel data stream and the output serial data stream are both synchronous clock domains, while in others it is necessary to When solving the problem of parallel-to-serial data conversion in the asynchronous time domain, designers usually use two methods: [0003] Method 1: When data is transferred across asynchronous clock domains, the input data flow can be temporarily stopped, and the next data will be processed after the handshake signal interaction across clock domains is successful. This method is obviously not suitable for those ...

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Problems solved by technology

[0005] In the application scenario of real-time and uninterrupted data stream processing, at this time, each parallel clock signal CLKP clock edge brings new parallel data to be processed, so the above method needs to use a large redundant space to cache data on the one hand. , in order to avoid data interruption during asynchronous transmission, that is, the required storage space must be greater than the amount of information in a single data transmission, sometimes even several times more, to ensure its reliability, so the circuit area is larger and the power In addition, the control logic similar to the asynchronous first-in-first-out queue (FIFO) structure needs pointers for reading and writing addresses and arithmetic circuits based on address pointers. The circuit structure is relatively complicated. Under the same conventional process and underlying device library resources , the circuit speed and reliability are obviously inferior to those of the design using this scheme, which is not conducive to some high-speed circuit applications in the digital-analog hybrid design

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