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High-threshold voltage gallium nitride (GaN) enhancement metal oxide semiconductor heterostructure field effect transistor (MOSHFET) device and manufacturing method

A high-threshold-voltage, enhancement-mode technology, used in semiconductor/solid-state device manufacturing, electrical components, semiconductor devices, etc., can solve problems such as lattice damage and low threshold voltage, reduce on-resistance, increase current density, The effect of improving device performance

Active Publication Date: 2012-03-21
SUN YAT SEN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] The purpose of the present invention is to overcome the disadvantages of low threshold voltage and lattice damage caused by plasma etching of ordinary hybrid MOSHFET devices, and provide a GaN-based enhanced MOSHFET device and its preparation method

Method used

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  • High-threshold voltage gallium nitride (GaN) enhancement metal oxide semiconductor heterostructure field effect transistor (MOSHFET) device and manufacturing method
  • High-threshold voltage gallium nitride (GaN) enhancement metal oxide semiconductor heterostructure field effect transistor (MOSHFET) device and manufacturing method
  • High-threshold voltage gallium nitride (GaN) enhancement metal oxide semiconductor heterostructure field effect transistor (MOSHFET) device and manufacturing method

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Embodiment 1

[0032] This example figure 1 A GaN high threshold voltage enhanced MOSFET device is given, including a substrate 1 and an epitaxial layer grown on the substrate 1, wherein the epitaxial layer includes a stress buffer layer 2, a GaN layer 3 and a heterogeneous layer from bottom to top. Structure barrier layer 4, etch heterostructure barrier layer 4 to GaN layer 3 in the gate area to form a groove, and selectively grow p-type GaN layer 6 on the groove, p-type GaN layer 6 and heterostructure An insulating dielectric layer 7 is deposited on the surface of the barrier layer 4, the insulating dielectric layer is etched on the source and drain regions of the heterostructure barrier layer 4, the gate metal 9 is evaporated on the gate region, and the source and drain regions are evaporated Plated ohmic contact metal8.

[0033] The heterostructure barrier layer 4 is one or any combination of AlGaN, AlInN, AlInGaN, and AlN materials, and the heterostructure barrier layer is an undoped l...

Embodiment 2

[0048] Such as figure 2 As shown, this embodiment provides a second structure of a GaN enhancement type MOSHFET device, which is roughly the same as the device structure of Embodiment 1. The difference is that the selective growth structure of the gate region is a double-layer epitaxial structure of u-GaN layer 10 and p-GaN layer 6 . The u-GaN layer can improve the crystal quality of the p-GaN layer and improve device performance.

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Abstract

The invention discloses a high-threshold voltage gallium nitride (GaN) enhancement metal oxide semiconductor heterostructure field effect transistor (MOSHFET) device and a manufacturing method. The device comprises a substrate (1) and an epitaxial layer grown on the substrate (1), and is characterized in that: the epitaxial layer comprises a stress buffer layer (2), a GaN layer (3) and a heterostructure barrier layer (4) sequentially upwards from the bottom; the heterostructure barrier layer (4) is etched to the GaN layer (4) to form a groove in a gate region; a p-type GaN layer (6) is selectively grown on the groove; an insulated dielectric layer (7) is deposited on the surfaces of the p-type GaN layer (6) and the heterostructure barrier layer (4) and etched in source and drain regions on the surface of the heterostructure barrier layer (4); a gate metal (9) is evaporated in the gate region; and an ohmic contact metal (8) is evaporated on the source and drain regions. The device provided by the invention has a simple structure, is simple in manufacturing process and high in stability, and can effectively increase a forward threshold voltage and simultaneously repair crystal lattices damaged by plasma treatment.

Description

technical field [0001] The invention relates to the field of semiconductor devices, in particular to a GaN high threshold voltage enhanced MOSFET device and a preparation method. Background technique [0002] Semiconductor power switching devices are necessary functional components in the process of power transmission and control. However, power switching devices made of third-generation semiconductor materials represented by GaN have wide bandgap, high breakdown electric field strength, high thermal conductivity, high saturation electron drift velocity, and high concentration of two-dimensional electron gas at the heterojunction interface. Excellent material properties have become a hot spot in the research of semiconductor power switching devices. Compared with traditional Si-based power devices, GaN-based power switching devices have the advantages of fast switching speed, low loss, and high heat resistance, and are ideal substitutes for next-generation energy-saving pow...

Claims

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Application Information

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IPC IPC(8): H01L29/778H01L29/10H01L29/78H01L21/335
Inventor 刘扬沈震张佰君
Owner SUN YAT SEN UNIV
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