Dual-edge-triggered state-retention scan flip-flop (DET-SRSFF)

Abstract

The invention relates to the technical field of integrated circuits and discloses a dual-edge-triggered state-retention scan flip-flop (DET-SRSFF), which is characterized by comprising a pulse generating circuit and a static-state latch circuit which are connected with each other, wherein the static-state latch circuit comprises a leakage feedback pulse structure. According to the invention, leakage feedback buffer (LFB) circuits in the pulse generating circuit of the traditional DET-SRSFF as well as a static-state latch and input-output circuit are improved, the structure of the LFB is simplified on the premise of completely maintaining the low-power-consumption advantage of the DET-SRSFF. In addition, the pulse generating circuit is modified, and generated redundant pulses are removed. Finally, a simulation result from high-precision simulation program with integrated circuit emphasis (HSPICE) shows that the improved structure has advantages in the aspects of both power consumption and speed. A power consumption lagged product is reduced by 19.56%, and the improved DET-SRSFF is more suitable to meeting requirements of the development of the integrated circuit on a trigger.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a dual-edge-triggered state-holding scannable flip-flop. Background technique [0002] With the decrease of the characteristic size of the integrated circuit process and the increase of the operating frequency of the circuit, reducing the leakage power consumption of the circuit has become the focus and difficulty of the integrated circuit design. The clock system consisting of sequential units (flip-flops and latches) and clock networks is one of the largest sources of power consumption in VLSI (Very Large Scale Integration) systems. Statistics show that about 30% to 60% of the leakage power is generated by the clock system, so reducing the power consumption of flip-flops has far-reaching significance (see literature [2]). In the literature [1], the dual-edge triggered state-retention scan flip-flop (DET-SRSFF) designed by H.Karimiyan, S.M.Sayedi and H.Saidi is aime...

AI Technical Summary

Problems solved by technology

[0007] 5. Due to the low-level technology, the high level of the latch may not be ideal, which will cause the PMOS tube connected to the output to not be completely turned off, increasing power consumption

[0019] But there is still a problem with the above structure: when going to sleep, CG will change from 0 to 1. It was expected that P will stop generating pulses immediately

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