A device and method for implementing fractional quadrature frequency division without inductance

Abstract

The present invention relates to a device and method for realizing fractional orthogonal frequency division without inductance. The VCO outputs a signal, the output end of the N+0.5 digital frequency division module is connected to the input end of the duty cycle correction module, and the output end of the duty cycle correction module is connected to the input end of the phase fine adjustment module. The device and method for implementing fractional orthogonal frequency division without inductance disclosed in the present invention have the advantages of low cost, low power consumption and high reliability.

Description

technical field [0001] The invention relates to the radio frequency field, in particular to a device and method for realizing fractional orthogonal frequency division without inductance. Background technique [0002] In radio frequency transceivers, due to the widespread use of integrated inductors, especially in single-chip integrated transceivers, it is necessary to properly consider the LO scheme to avoid crosstalk. Among them, the traction effect of PA on VCO is particularly obvious. In order to avoid the frequency of the PA transmitted signal and its higher harmonics from pulling the frequency of the VCO, it is necessary to make the VCO work at a frequency that is a fractional multiple of the local clock (LO), such as 1.5 or 2.5 times. The transceiver requires the LO to provide two orthogonal clocks. The traditional pure digital fractional frequency division method cannot achieve a clock output with a 50% duty cycle and a 90° phase difference. If an inductor is used, t...

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Problems solved by technology

[0004] However, the above-mentioned schemes have many disadvantages: 1. The schemes containing inductors have high cost and large chip area; 2. The schemes based on VCDL without inductors have complex structures, which need to be corrected to generate eight-phase clocks with equal phases and then processed, and the power consumption is low. 3. There are three phase-shifting loops, and the reliability is not very good. The mismatching superposition of the other three phase-shifting loops will also cause IQ mismatch. 4. The above non-inductor solutions are only suitable for 1.5 frequency division, not suitable for other decimal frequency division

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