Video processing device and method
A video processing and equipment technology, applied in the field of video processing, can solve the problems of increased decoding speed, large access delay, and high bandwidth requirements, and achieve the effect of saving bandwidth, saving circuit area, and speeding up decoding speed
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Embodiment 1
[0056] Such as Figure 2a As shown, a video processing device provided by an embodiment of the present invention includes: a video decoder and an external memory, wherein:
[0057] The video decoder is used to decode the original video code stream, and the decoding is performed in units of macroblocks, with blocks as the basic operation object;
[0058] External memory 20, used for storing reference frame data;
[0059] Specifically, the video decoder includes: a parser 21, an inverse quantization / inverse transformation unit 22, an address generator 23, a reference data reading unit 24, a motion compensation unit 25, and a reconstruction unit 26, and also includes a data cache 27, a tag cache device 28, wherein:
[0060] The parser 21 is connected to the inverse quantization / inverse transformation unit 22, the address generator 23 and the reference data reading unit 24 respectively, and is used to obtain the position information, the motion vector and the position informatio...
Embodiment 2
[0092] In the first embodiment, the data blocks in the reference frame are gradually buffered into the data buffer 27 according to the reference blocks required by each macroblock, but when the decoding of a macroblock line is completed, the reference data buffered in the data buffer 27 is basically The above are all the reference data of the rightmost macroblocks of this macroblock row, and the reference data of the left few macroblocks of the next macroblock row that needs to be decoded may not be able to find the required cache in the data buffer data. Therefore, in order to make full use of the spatial correlation of the decoded data, the second video decoding device provided by the embodiment of the present invention includes two levels of cache, the cache control of the first level cache and the Figure 2a The cache control principle of the middle data buffer 27 is the same. What is cached in the second-level cache is the reference data of the reference blocks within the...
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