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Method and device for reducing interconnection line model of great quantity of ports

A technology of model reduction and interconnection, which is applied in special data processing applications, instruments, electrical digital data processing, etc., can solve the problems of long simulation time of models, achieve short simulation time, high efficiency, and ensure passivity Effect

Active Publication Date: 2012-02-01
FUDAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In some cases, there are even instances where the reduced model takes longer to simulate than the original model

Method used

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  • Method and device for reducing interconnection line model of great quantity of ports
  • Method and device for reducing interconnection line model of great quantity of ports
  • Method and device for reducing interconnection line model of great quantity of ports

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0052] A phase-locked loop circuit is composed of 836 MOS tubes. After extracting the parasitic parameters, there are 44726 resistor-capacitor linear elements, and the number of circuit nodes is 7314. By dividing into linear sub-circuits and nonlinear sub-circuits in step 201, it can be obtained that the number of ports of the linear sub-circuit is 1326. The original circuit simulation time was 14 seconds. Setting the maximum number of nodes in the subset in step 203 to 10, the linear subcircuit can be divided, and a part of the result obtained by division is as follows Figure 6 As shown in , where the ellipse represents the port of the linear circuit, the rectangle represents the internal node of the linear circuit, and the number represents the number of the sub-set to which the node belongs after division. It can be seen that the nodes connected together are divided into the same subset, and such division has physical meaning.

[0053] In order to compare the proposed me...

Embodiment 2

[0058] A multiplier circuit is composed of 3685 MOS tubes. After extracting the parasitic parameters, there are 208497 resistor-capacitor linear elements, and the number of circuit nodes is 18112. By dividing into linear sub-circuits and nonlinear sub-circuits in step 201, it can be obtained that the number of ports of the linear sub-circuit is 3685. The original circuit simulation time is 190 seconds.

[0059]In order to compare the proposed method with the elimination-based method SIP, the present invention uses the above-mentioned embodiments using AMOR and Z.Ye, D.Vasilyev, Z.Zhu and J.R.Phillips at the 1999 International Conference on Computer Aided Design (ICCAD) published the paper "Sparse implicit projection (SIP) for reduction of general many-terminal networks" proposed SIP method (Z.Ye, D.Vasilyev, Z.Zhu, and J.R.Phillips, "Sparse implicit projection (SIP) for reduction of general many-terminal networks," in Proc.ICCAD'2008) two methods for model reduction, and then...

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Abstract

The invention belongs to the field of integrated circuits, and relates to a method and device for reducing an interconnection line model of a great quantity of ports. The method comprises the following steps of: constructing an undirected graph according to connection relationship of resistors and capacitors of an interconnection line circuit of a great quantity of ports, partitioning the undirected graph by utilizing a spectrum partitioning method, and finally carrying out coarse graining on nodes in a same partition set, thus obtaining a reduced circuit. The device comprises an input unit, an output unit, a program storage unit, an external bus, a memory, a storage management unit, an input and output bridging unit, a system bus and a processor; and an AMOR program of the reduction method can be realized through storage of the program storage unit. According to the invention, model reduction is carried out on the interconnection line of a great quantity of the ports without introduction of nonzero components, and the reduced model is ensured to be shorter in simulation time and higher in efficiency, and simultaneously the resistance value and capacitance of the obtained reduced circuit are positive values, thus having physical realizability and ensuring the passiveness of the reduced circuit.

Description

technical field [0001] The invention belongs to the field of integrated circuits, and in particular relates to a method and device for reducing the order of an interconnect line model with a large number of ports. Background technique [0002] Interconnect networks naturally have a large number of ports. An integrated circuit can be divided into active devices and interconnecting lines. Active devices usually have a certain number of pins, and interconnect lines connect these pins together to form an integrated circuit with a certain function. A single interconnect may connect thousands of pins and therefore have thousands of ports. At the same time, due to the existence of the coupling effect in the integrated circuit, even if the number of ports of a single interconnection line is not very large, the number of ports of the linear network formed by the coupling of the interconnection lines will still be large. [0003] The scale of interconnection circuits is very large,...

Claims

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Application Information

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IPC IPC(8): G06F17/50
Inventor 苏仰锋曾璇杨帆宗可张玉洁
Owner FUDAN UNIV
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