Process for reducing chemical-mechanical polishing crack on buried layer cavity silicon-on-insulator (SOI) wafer

Abstract

The invention discloses a process for reducing chemical-mechanical polishing cracks on a buried layer cavity silicon-on-insulator (SOI) wafer, belonging to the technical field of microelectronic material processes. Aiming at reducing the thickness of the buried layer cavity SOI wafer through chemical-mechanical polishing, the process mainly comprises the steps of pressure setting, bonding, rough grinding and fine polishing for completing the fabrication of the buried layer cavity SOI wafer. Pressure in a bonding chamber and steps for two stages of chemical-mechanical polishing, i.e. coarse grinding and fine polishing are set according to the final thickness of the top layer silicon film of the SOI wafer. By setting the pressure in the bonding chamber, thermal-induced top layer silicon film deformation in a chemical-mechanical polishing process can be balanced, the cracks on the top layer silicon film of the SOI wafer can be avoided or reduced, the consistency of the thickness of the top layer silicon film is improved, the product quality is controlled very well and the processing cost is reduced.

Description

technical field [0001] The invention relates to a semiconductor material preparation process, in particular to a process for reducing the cracking of a top silicon film during the polishing process of a buried layer cavity type SOI wafer, and belongs to the technical field of microelectronic material technology. Background technique [0002] MEMS technology is developing rapidly, and SOI MEMS technology is getting more and more attention. In SOIMEMS technology, it is often necessary to manufacture patterns in the buried layer structure to form a buried layer void SOI structure, which has led to the development of buried layer void SOI wafer products. Okmetic Company of Finland and IceMOS Company of the United States have begun to sell buried-layer cavity-type SOI wafers (Cavity SOI) products. The 48th Institute of China Electronics Technology Group Corporation, the 24th Institute of China Electronics Technology Group Corporation and Shanghai Simgui Technology have all maste...

AI Technical Summary

Problems solved by technology

[0006] In order to overcome the defects that the existing SOI wafer preparation process makes the top layer silicon film at the cavity position in the buried layer cavity type SOI wafer easy to deform or even rupture, resulting in poor consistency of the top layer silicon film thickness, decline in product quality or even scrapping, the present invention aims at In providing a process for reducing chemical mechanical grinding cracks of buried layer void type SOI wafers, the process can effectively reduce SiO 2 Breakage of the silicon film on the top layer of SOI wafers with buried voids during the CMP process, improving the SDB (Silicon-silicon Direct Bonding) process, and improving the quality and yield of SOI wafers with buried voids

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