Time-to-voltage converter-based high-precision pulse width comparison device

Abstract

The invention discloses a time-to-voltage converter-based high-precision pulse width comparison device. The device disclosed by the invention provides a rapidly automatic frequency correction device based on a time-to-voltage converter; improvement is made generally on the basis of an automatic frequency correction device based on frequency comparison and measurement, a time to voltage converter-bilateral phase frequency detector (TVC-PFD), a time to voltage converter-charge pump (TVC-CP), a time to voltage converter-voltage comparator (TVC-CMP) and a time to voltage converter-capacitor array regulating module (TVC-AFC) are added. The capacitor array configuration can be adjusted according to comparison results so as to find out optimal capacitor array configuration. According to the invention, the device can discriminate frequency difference between a reference clock and a feedback clock with a higher precision, shorten the comparison frequency and further reduce the locking time of a phase lock loop, thus the need of a modern communication system on fast clock frequency switching can be satisfied.

Description

technical field [0001] The invention relates to an automatic frequency calibration circuit for a phase-locked loop of a radio frequency integrated circuit chip. Background technique [0002] At present, in modern communication systems, radio frequency chips often need to cover a wide frequency range, which is beyond the range covered by VCO (Voltage control oscillator voltage-controlled oscillator) by adjusting the voltage, PLL phase-locked loop (Phase Lock Loop lock Phase loop) provides the local oscillator for the RF chip, so it needs to be able to lock normally in a large frequency range. By adding an adjustable capacitor array to the VCO, the adjustable range of the VCO frequency is increased, and the VCO can lock and maintain a small VCO sensitivity in a large frequency range, ensuring that the phase noise of the system will not deteriorate. After the PLL system is powered on and the VCO and Divider (frequency divider) are stable, the reference clock and the frequency ...

AI Technical Summary

Problems solved by technology

However, since the difference between the reference clock frequency and the feedback clock frequency is not large, it takes a long time to count to divide the frequency difference, resulting in too long time for the phase-locked loop output clock to stabilize and cannot meet the requirements for fast switching of clock frequency in the communication system.

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