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Flash memory devices having multi-bit memory cells therein with improved read reliability

A technology for storage devices and storage cells, which is applied in read-only memory, static memory, digital memory information and other directions, and can solve problems such as voltage window limitations

Active Publication Date: 2011-08-10
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] However, the voltage window available for the threshold voltage distribution is limited

Method used

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  • Flash memory devices having multi-bit memory cells therein with improved read reliability
  • Flash memory devices having multi-bit memory cells therein with improved read reliability
  • Flash memory devices having multi-bit memory cells therein with improved read reliability

Examples

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Embodiment Construction

[0024] Preferred embodiments of the present inventive concept will be described in more detail below with reference to the accompanying drawings. However, inventive concepts may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. Like reference numbers refer to like elements throughout. The circuit configuration and read operation of the flash memory device according to the inventive concept to be described below are merely exemplary, and various changes can be made to it in form and detail without departing from the spirit and scope of the inventive concept. .

[0025] figure 1 is a schematic structural diagram illustrating a memory system 1000 including a flash memory 100 according to an example embodiment of the inventive concepts.

[0026...

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Abstract

Integrated circuit memory devices include an array of nonvolatile N-bit memory cells, where N is an integer greater than one. Control circuitry is also provided to reliably read data from the N-bit memory cells. This control circuitry, which is electrically coupled to the array, is configured to determine, among other things, a value of at least one bit of data stored in a selected N-bit memory cell in the array. This is done by decoding at least one hard data value and a plurality of soft data values (e.g., 6 data values) read from the selected N-bit memory cell using a corresponding plurality of unequal read voltages applied to the selected N-bit memory cell during a read operation.

Description

[0001] Priority Application Citation [0002] This application claims priority to Korean Patent No. 10-2010-0011554 filed on Feb. 8, 2010, the contents of which are incorporated herein by reference. technical field [0003] The present invention relates to semiconductor memory devices, and more particularly, to flash memory devices and methods of operating the same. Background technique [0004] Semiconductor memory devices are generally classified into volatile memory devices (eg, DRAM and SRAM) and nonvolatile memory devices (eg, EEPROM, FRAM, PRAM, MRAM, and flash memory). A volatile memory device loses data stored therein when its power supply is interrupted, while a nonvolatile memory device retains data stored therein even when its power supply is interrupted. In particular, flash memory devices are widely used as storage media in computer systems due to their fast programming speed, low power consumption, and large storage capacity. [0005] In a flash memory device...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/02G11C16/26
CPCG11C11/5642G11C16/26G11C16/0483G11C16/3418
Inventor 蔡东赫韩真晚
Owner SAMSUNG ELECTRONICS CO LTD
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