Multi-project wafer cutting method supporting constraint and limitation on positions of chips

Abstract

The invention discloses a multi-project wafer cutting method supporting constraint and limitation on the positions of chips, and the method comprises the following steps: performing relative and absolute position constraint on a mask plate against the chips according to actual production and testing requirements; re-adjusting and defining a general objective equation of a simulated annealing algorithm in the layout planning method; and simultaneously enabling the chips which are in the same or similar size and need to be placed in the adjacent positions to attribute to a same layout group, thereby ensuring that the chips or sub-layout groups in the same layout group to be always positioned in the adjacent positions, effectively reducing the iteration number and the time of the simulated annealing algorithm, realizing automation of layout planning of the chips under the constraint and the limitation in the specific positions, further greatly reducing the area of the mask plate, dividing more mask plates on one wafer by cutting, and greatly reducing the corresponding cost.

Description

technical field [0001] The invention relates to a wafer cutting method, in particular to a multi-item wafer cutting method that supports chip positions being restricted. Background technique [0002] Multi Project Wafer (Multi Project Wafer, referred to as MPW), is to put a variety of integrated circuit designs with the same process on the same mask (Reticle / Mask, also known as reticle). After the manufacturing is completed, each Dozens of chip samples can be obtained for a design project, which is enough for experiments and tests in the prototype (Prototype) design stage. The manufacturing cost is shared by all the projects participating in the multi-project wafer according to their respective chip areas, and the cost is only 5%-10% of the cost of prototype manufacturing for a single project, which greatly reduces product development risks. The threshold for cultivating integrated circuit design talents and the threshold for small and medium integrated circuit design compa...

AI Technical Summary

Problems solved by technology

Therefore, the traditional chip automatic layout planning technology does not support this function, and thus cannot achieve the purpose of minimizing the area of ​​the mask plate formed by chip arrangement and combination; It is more difficult to achieve the requirement of minimizing the mask area as much as possible under the condition that the chip is limited by the position constraints.

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