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FPGA implementation device for solving least square problem based on Cholesky decomposition

A least-squares, problem-based technology, applied in the field of FPGA implementation devices, can solve the problem that computing efficiency cannot meet real-time and embedded applications.

Active Publication Date: 2013-03-20
HARBIN INST OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The purpose of the invention is to solve the problem that the computing efficiency of existing PCs cannot meet real-time and embedded applications, and provide a FPGA implementation device based on Cholesky decomposition to solve the least squares problem

Method used

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  • FPGA implementation device for solving least square problem based on Cholesky decomposition
  • FPGA implementation device for solving least square problem based on Cholesky decomposition
  • FPGA implementation device for solving least square problem based on Cholesky decomposition

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specific Embodiment approach 1

[0009] combine figure 1 Describe this embodiment, this embodiment comprises matrix input interface module 6 to be sought, decomposition module 1 and solution module 2, the output end of matrix input interface module 6 to be sought is connected to the input end of decomposition module 1, the output end of decomposition module 1 Connected to the input of solving module 2.

[0010] For an n-dimensional linear equation system, set: Ax=b where A is an n×n-dimensional matrix, x is an n-dimensional solution vector to be found, and b is an n-dimensional column vector. If you want to solve the solution vector x of the linear equation system, you need to solve the inverse of the n×n-dimensional matrix A. There are many methods for finding the inverse matrix, such as the adjoint matrix method, elementary transformation method, and block matrix method introduced in linear algebra. , there are also some inversion methods commonly used in engineering, such as Gauss-Jordan elimination metho...

specific Embodiment approach 2

[0022] combine figure 2 , image 3 and Figure 4 Describe this embodiment, the decomposition module 1 of this embodiment includes PE_D module 3, multiple PE_L operation modules 4, multiple decomposition result generation modules L ij 15, the control module 7 and the switch module 8, the output end of the matrix input interface module 6 to be requested is connected to an input end of the PE_D module 3, and the output end of the PE_D module 3 is respectively connected to the input ends of a plurality of PE_L operation modules 4, and the multiple The data transmission end of each PE_L operation module 4 is respectively connected with the corresponding decomposition result generation module L ij The data transmission end of 15 is connected, and the output end of control module 7 is connected with the control signal input end of switch module 8, and the data input end of switch module 8 is once connected with a decomposition result generation module L ij The output end of 15...

specific Embodiment approach 3

[0041] combine Figure 5 and Figure 6 Describe this embodiment, the solution module 2 of this embodiment includes a control unit 16, a plurality of PE units 5, a subtractor 9, RAM_z10, a gate switch 11, RAM_b12, a multiplier 13 and a decomposition result generation module 1 / dr14, a plurality of One input end of the PE unit 5 is respectively connected to the decomposition result generating module L ij 15 result output end, the output end of control unit 16 is connected to the control input end of gating switch 11, and gating switch 11 connects the data transmission end of one PE unit 5 at a time, and the output end of gating switch 11 is connected in subtractor A data input end of 9, the data output end of subtractor 9 are respectively connected to RAM_z10 and a data input end of multiplier 13, and the output end of decomposition result generation module 1 / dr14 is connected to another data input end of multiplier 13, The input end of the decomposition result generation modu...

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Abstract

The invention relates to a FPGA (Field Programmable Gate Array) implementation device for solving least square problem based on Cholesky decomposition, which is suitable for solving the least square problem and settles the problem that computation efficiency of PC (Personal Computer) cannot satisfy real-time and embedded applications; the device comprises a to-be-solved matrix input interface module, a decomposing module and a solving module, wherein an output end of the to-be-solved matrix input interface module is connected to an input end of the decomposing module, and the output end of the decomposing module is connected to the input end of the solving module in order to satisfy real-time, low-consumption and embedded applications.

Description

technical field [0001] The invention relates to an FPGA realization device for solving the least square problem based on Cholesky decomposition. Background technique [0002] The problem of solving the solution of linear equations can be regarded as the solution of the least squares problem. At present, it is mainly implemented on a PC with a von Neumann structure. The computing efficiency of a PC cannot meet the needs of real-time and embedded applications; using ASIC (Application Specific Integrated Circuit) method can improve computing efficiency, but has poor applicability and high cost. Contents of the invention [0003] The purpose of the present invention is to provide a FPGA implementation device for solving the least squares problem based on Cholesky decomposition in order to solve the problem that the computing efficiency of the existing PC cannot meet real-time and embedded applications. [0004] The FPGA implementation device for solving the least squares prob...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/11
Inventor 彭宇刘大同乔立岩王少军刘琦仲雪洁王建民
Owner HARBIN INST OF TECH
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