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Double-processor borne computer

A technology of onboard computer and dual processors, applied in the field of data processing, to avoid crossover, ensure stability, and eliminate single point failures

Inactive Publication Date: 2013-02-06
HARBIN INST OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The present invention proposes a dual-processor on-board computer in order to solve the unavoidable ping-pong switching problem existing in the arbitration method of the existing dual-processor on-board computer and the problem of ping-pong power grab

Method used

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Experimental program
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specific Embodiment approach 1

[0018] Specific embodiment 1: The dual-processor on-board computer described in this embodiment is a on-board computer with an arbitration module. The on-board computer is composed of a master computer, a slave computer, a power supply and arbitration module, an IO module, and a backplane. The host computer, the slave computer, the power supply and the arbitration module, and the IO module are all fixed on the backplane, and the backplane is also fixed with a control enable signal line, a power line, a master CPU data address bus and a slave CPU data address bus, so The power supply and arbitration module is composed of a DC / DC power conversion module for the main CPU, a DC / DC power conversion module for the slave CPU, and an arbitration module; a DC / DC power conversion module for the slave CPU; the host computer includes a main CPU module and a main The IO control module of the CPU, the main CPU uses a DC / DC power conversion module to provide isolated DC power supply for the IO...

specific Embodiment approach 2

[0031] Specific implementation manner 2: see figure 2 This embodiment will be described. This embodiment is to further limit the dual-processor on-board computer described in the first embodiment. The star-arrow separation signal in this embodiment is implemented by the following hardware circuit: the circuit includes a magnetic latching relay, multiple diodes, and multiple The first coil of the magnetic latching relay and the current-limiting resistor are connected in series between the positive pole of the coil power supply and the star and arrow separation signal HJFL. The coil is connected in series with two diodes to form a coil protection and discharge circuit. The coil corresponds to The moving contact of the first group of single-pole double-throw switches is the star-arrow separation signal output terminal. The normally closed static contact of the first group of single-pole double-throw switches is connected to the digital power ground, and the normally open contact i...

specific Embodiment approach 3

[0035] Specific implementation manner three: see image 3 This embodiment will be described. This embodiment is a further limitation to the dual-processor on-board computer described in the first embodiment. The ground remote control autonomous cut-off enable signal in this embodiment is realized by the following hardware circuit: It consists of a resistor and a plurality of diodes. One end of the magnetic latching relay is connected to the anode of the coil power supply through a current-limiting resistor, and the other end of the coil is simultaneously connected to the anodes of three diodes, and the cathodes of the three diodes are respectively It is the output terminal of the auto-cutting enable signal, the output terminal of the power-on reset signal and the output terminal of the system reset signal; the first coil is connected in series with two diodes to form a coil protection discharge circuit; the first coil corresponds to the first set of single-pole double-throw swit...

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Abstract

The invention discloses a double-processor borne computer which relates to a double-processor technology applied in the aerospace field. The double-processor borne computer solves the problem that ping pong switch and ping-pong right robbing are difficult to avoid in the arbitration method in a borne computer of the traditional double-processor borne computer. A master computer, a slave computer, a power supply, an arbitration module and an IO module of the double-processor borne computer are all fixed on a base plate and connected mutually through data address buses, signal wires and power wires on the base plate, wherein the logical relation of the arbitration module is that: the working condition of the master computer is that an star arrow separation signal is ineffective, an output enable signal of the slave computer is ineffective, and a ready signal of the master computer is effective, or a remote control switch master computer signal is effective; and the working condition of the slave computer is that: an output enable signal of the master computer is ineffective, a generator tripping enable flag is effective, a ready signal of the master computer is ineffective, and a ready signal of the master computer is effective; or an automatic generator tripping signal of the master computer is effective, and the generator tripping enable flag is effective; or a remote control switch slave computer signal is effective.

Description

Technical field [0001] The invention relates to the technical field of data processing, in particular to a dual processor for aerospace applications, a spaceborne computer with autonomous arbitration, automatic switching, and automatic power-off configuration and an implementation method thereof. Background technique [0002] With the continuous advancement of micro-spacecraft technology, modern small satellites continue to increase in size, weight, cost, and power consumption, while their functions continue to increase. It is required that the existing on-board computer not only can integrate a large number of hardware circuits and computing units on a single chip, but also can flexibly configure the internal circuit structure and external interfaces of the computer according to task requirements, so that it has powerful computing power and high integration. [0003] In the working process of the existing dual-processor on-board computer, it is necessary to ensure the effective fu...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F15/80
Inventor 兰盛昌马玉海于文进潘瑞张锦绣张相宇丁玉叶
Owner HARBIN INST OF TECH
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