Data bus in multi-kernel processor chip

Abstract

The invention relates to a data bus in a multi-kernel processor chip, which comprises route control units (102) in one-to-one correspondence to a kernel (101); a kernel data transmission bus is arranged between each route control units (102) and the kernel (101) and two, three or four pairs of route data transmission buses are arranged between adjacent route control units (102). The route control unit (102) further has a static route exchange unit and a dynamic route exchange unit. The bus network structure realizes agile transfer of data variables while realizing data stream transfer with high throughput rate simultaneously.

Description

technical field [0001] The invention relates to a bus network structure in a multi-core processor chip, in particular to a design structure of a data communication bus between cores. Background technique [0002] As microelectronics technology gradually enters the nanometer level, the ensuing problem is that the width of the copper wires inside the processor is too thin, so that the electrons between the wires attract each other to generate electronic transitions; the thinner wire width means The failure rate has increased significantly; the power consumption of the chip has seriously affected the performance of the processor. As the microscopic limit that human beings can grasp, it will be difficult to use thinner line width and smaller circuits to improve the performance of processors in the future, that is, relying on the advancement of electronic technology can no longer continue to support the performance of processors. keep improve. [0003] Therefore, relying on arc...

AI Technical Summary

Problems solved by technology

[0019] (1) Multi-core processors using static routing buses generally have poor flexibility and low utilization of the bus, and the overall performance of the chip can only be brought into play for specific applications;

[0020] (2) Although the data throughput rate of the static network is high, in practical applications, the input / output operation of the kernel to data often becomes the bottleneck that affects the performance of the static routing network;

[0021] (3) If the multi-core processor using the dynamic routing bus is aimed at a tile structure with strong scalability, it will lead to complex routing control. Once the data channels of dynamic routing increase, the power consumption will be very large; for other structures, The data needs to be transmitted along the route in a single cycle, and the data transmission delay is proportional to the length of the route, so that the main frequency of the entire chip will not be very high;

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