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Semiconductor device, basic cell and semiconductor integrated circuit device

A basic unit and integrated circuit technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve the problem of metal filling rate decline, so as to suppress the decline of manufacturing yield and suppress the through-hole metal The effect of the drop in fill rate

Active Publication Date: 2011-01-26
SOCIONEXT INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Thus, with Figure 25 In the same case, there is a possibility that the metal filling rate may decrease in the metal filling step of the via hole

Method used

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  • Semiconductor device, basic cell and semiconductor integrated circuit device
  • Semiconductor device, basic cell and semiconductor integrated circuit device
  • Semiconductor device, basic cell and semiconductor integrated circuit device

Examples

Experimental program
Comparison scheme
Effect test

no. 1 Embodiment approach

[0088] figure 1 It is a configuration diagram showing wiring and vias under wiring according to the first embodiment. In this figure, (a) is a plan view showing the arrangement position and shape of the wiring 1 and the via hole 3 below it, (b) is a plan view showing the shape of the wiring 1 alone, and (c) is a plan view showing the through hole 3 alone. (d) is a via pattern 4 used to mask the via hole 3 in the manufacture of a semiconductor device, (e) is a plan view showing the arrangement position and shape of the wiring 1 and the via hole 8 below it. , (f) is a plan view showing the shape of the via hole 8 alone, and (g) is a via hole pattern 9 used for mask formation of the via hole 8 at the time of semiconductor device manufacture.

[0089] In the wiring of a semiconductor device, there are generally a plurality of curved regions, that is, bent portions 2 , on the wiring path. For example figure 1 As shown in (b), the L-shaped wiring 1 as the first wiring has a ben...

no. 2 Embodiment approach

[0099] image 3 It is a configuration diagram showing wiring and vias under wiring according to the second embodiment. In this figure, (a) is a plan view showing the arrangement position and shape of the wiring 1 and the via holes 3 and 31 therebelow, (b) is a plan view showing the shape of the wiring 1 alone, and (c) is showing the through hole. 3, 31 is a plan view of the shape of a single body, (d) is a via hole pattern used for mask formation of the via holes 3, 31 in the manufacture of a semiconductor device. image 3 structure with figure 1 roughly the same as figure 1 The same structural elements are attached to the figure 1 same symbol.

[0100] exist image 3 In the structure of , between the wiring 1 and the second wiring (not shown) arranged under the wiring 1, a via 31 as a second via is formed in addition to the via 3 so that the via 31 includes a bend. Section 2 area. The through hole 31 has the notch part 5 similarly to the conventional through hole. ...

no. 3 Embodiment approach

[0104] Figure 5 It is a configuration diagram showing the wiring and the via hole under the wiring according to the third embodiment. In this figure, (a) is a plan view showing the arrangement position and shape of the wiring 13 and the through hole 41 below it, (b) is a plan view showing the shape of the wiring 13 alone, and (c) is a plan view showing the shape of the through hole 41 alone. In the plan view of the body shape, (d) is a via pattern 4 used for masking the via hole 41 during semiconductor device manufacture, and (e) to (g) are plan views showing examples of other wiring shapes.

[0105] exist Figure 5 In the structure of , between the wiring 13 as the first wiring and the second wiring (not shown) arranged in the lower layer of the wiring 13, using Figure 5 The circular through hole pattern 4 shown in (d) is larger than the bent portion 2 to form a through hole 41 as a first through hole.

[0106] Such as Figure 5 As shown in (b), the wiring 13 has a bent...

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PUM

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Abstract

A semiconductor device provided with an interconnect (1) comprising a bent part (2), a first interconnect region (1a) extending from the bent part (2) to the X-direction, and a second interconnect region (1b) extending from the bent part (2) to the Y-direction. A via (3) is formed under the interconnect (1). The via (3) is formed at the first interconnect region (1a) so as to not overlap with the region of the bent part (2). The length (x) of the via (3) in the X-direction is longer than the length (y) in the Y-direction, and the two ends of the same in the Y-direction overlap with the two ends of the first interconnect region (1a) in the Y-direction.

Description

technical field [0001] The present invention relates to the structure of a semiconductor device corresponding to a fine process, and particularly relates to the structure of wiring and connection holes (via holes) under the wiring. Background technique [0002] Conventionally, a dual damascene (Dual Damascene) method is known, in which a wiring groove is formed in an insulating film, a via hole is formed at the bottom of the wiring groove, and a conductive material is embedded in the wiring groove and the via hole to form wiring and a contact part at the same time. . In this dual damascene method, the so-called trench first method is known. In this trench first method, a via pattern is formed by photolithography on a hard mask on which a wiring pattern is formed, and then the via hole is formed by etching. and wiring trenches (for example, refer to Patent Document 1). [0003] use Figure 25 The structures of wiring and vias in the conventional trench-first dual damascene ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/82H01L21/3205H01L21/768H01L21/822H01L23/52H01L27/04
CPCH01L23/5226H01L27/0207H01L2924/0002H01L27/11807H01L23/481H01L23/528H01L2924/00
Inventor 一柳美和上原裕之西村英敏
Owner SOCIONEXT INC
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