Method and system for counting data packets

Abstract

The disclosure provides a method for counting data packets, which includes the following steps: counting packet pulse signals when a low bit counter is in a count state, and sending a carry signal when the low bit counter is full; and acquiring data from an address of a Random Access Memory (RAM) corresponding to the low bit counter which sends the carry signal, adding 1 to the acquired data and then writing the added data into the address. The disclosure also provides a system for counting data packets. According to the technical scheme of the disclosure, the occupancy rate of logical resources is reduced while the counting of the data packets in a network is finished at a high speed.

Description

technical field [0001] The invention relates to network information management technology in the field of network systems, in particular to a method and system for counting data packets. Background technique [0002] In a multi-channel network system, in order to eliminate the fault of one of the channels, or to bill the data flow in the network system, it is necessary to classify the data packets, and on this basis, respectively count the various channels in the network system. The number of packets of type sent and received. [0003] In the prior art, two methods are usually used to calculate the number of data packets in the network system. The first method is implemented by using registers. For example, there are n channels in the network system, and each channel has m types of data packets. Each type of data packet requires a k-bit counter, because a k-bit register can implement a A k-bit binary counter, so at least n*m*k registers are required to count data packets; ...

AI Technical Summary

Problems solved by technology

The advantage of the first implementation method is that the counting speed is fast, but the disadvantage is that if counting multiple channels and multiple data packets, because more counters and lookup tables are used, it takes up a lot of logic resources

The advantage of the second implementation method is that it takes up less register resources, but since it takes at least 3 clock cycles to read and write RAM, if the counting pulses are dense, the operation speed of the counter will not meet the needs of high-speed technology

However, there are two defects in this method: one is to only use RAM to realize counting, and it takes at least 3 clock cycles to read and write data in RAM. The application of this patent requires within 96 clock cycles, so statistics are needed The number of data packets cannot exceed 32, otherwise there will not be enough time for processing, so it has great limitations; the second is that although this method can count data packets for multiple channels at the same time, it cannot count data packets for a single channel If a channel needs to restart counting, the entire system can only be reset, thus reducing the flexibility of the system

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