High mains rejection ratio low dropout voltage linear voltage regulator with feedforward transconductance

Abstract

The invention belongs to the technical field of integrated circuits and specifically relates to a high mains rejection ratio low dropout voltage linear voltage regulator with a feedforward transconductance, which consists of an error amplifier, a buffer, a PMOS pass transistor, a feedforward transconductance, two feedback resistors and a filter capacitor, wherein the error amplifier is a current mirror amplifier consisting of a tail current source, a PMOS input differential pair and three groups of current mirrors. The mains voltage fluctuation influences the output mainly via two paths of the PMOS pass transistor and the parasitic resistor of and PMOS pass transistor. The feedforward transconductance transforms the perturbation of the mains voltage into the perturbation of the current, and then the perturbation of the current is transformed into the in-phase voltage perturbation of the grid of the pass transistor via the parasitic resistor of the error amplifier. The influence of the mains voltage perturbation on the output can be eliminated by the control of the gain of the feedforward transconductance so as to realize high mains rejection ratio. The invention can optimize the mains rejection ratio within a wider range of load current and does not reduce the efficiency of the low dropout voltage linear voltage regulator.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a low-dropout linear regulator (LDO) with high power supply rejection ratio and feedforward transconductance. Background technique [0002] LDO is the core module in power management, which mainly provides power for noise-sensitive circuits such as analog circuits and radio frequency circuit enhancements. Therefore, the power supply rejection ratio is one of its key performance parameters. At present, most commercial LDO chips with high power supply rejection ratio adopt LDO cascading, which directly leads to low efficiency of LDO. Although many high power supply rejection ratio LDO solutions have appeared in papers in recent years, most of them come at the expense of increased output voltage noise, increased circuit complexity, and lower load current. Therefore, it is of great application significance to design a high power supply rejection ratio that...

AI Technical Summary

Problems solved by technology

At present, most commercial high power supply rejection ratio LDO chips use LDO cascading, which directly leads to low efficiency of LDO

Although many high power supply rejection ratio LDO solutions have appeared in papers in recent years, most of them come at the cost of increased output output voltage noise, increased circuit complexity, and lower load current

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