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Sigma-delta fraction N frequency comprehensive device behavior level modeling method

A technology of frequency synthesizer and modeling method, applied in the fields of instruments, automatic control of power, electrical digital data processing, etc.

Active Publication Date: 2010-09-15
江苏创通电子股份有限公司
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  • Abstract
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  • Application Information

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Problems solved by technology

[0006] The technical problem to be solved by the present invention is to improve the behavior-level modeling method of the traditional phase-locked loop system in the prior art, especially the modeling of the noise source, so that it can be analyzed in the early stage of the design that the frequency synthesizer will affect the whole wireless The noise floor of the communication system and the impact of the overall system sensitivity

Method used

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  • Sigma-delta fraction N frequency comprehensive device behavior level modeling method
  • Sigma-delta fraction N frequency comprehensive device behavior level modeling method
  • Sigma-delta fraction N frequency comprehensive device behavior level modeling method

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Embodiment

[0075] In this embodiment, a Σ-Δ fractional-N frequency synthesizer is modeled using VHDL-AMS language, and its performance is simulated by the simulator ADMS. In this embodiment, the modules including the oscillator, phase-frequency detector, charge pump, VCO, filter, frequency divider, and Σ-Δ modulator included in the frequency synthesizer are modeled at the behavioral level, where the local oscillator Phase-frequency detectors, charge pumps, VCOs, filters, and frequency dividers are phase-locked loop systems. Some nonlinear effects, such as charge pump asymmetry, dead zone effects, and jitter noise are modeled. Of all the key performance metrics for a PLL system, phase noise is the most critical because it increases the noise floor and degrades the system's sensitivity, and it is also a more difficult part to model. In order to model the PLL system more accurately, different jitter noise sources are modeled, and the Σ-Δ modulator, which mainly affects the phase noise of t...

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Abstract

The invention relates to a frequency comprehensive device behavior level modeling method considering noise source affect, belonging to the technical field of wireless transmission communication. In order to improve the traditional behavior level modeling method carried out for a sigma-delta fraction N frequency comprehensive device in the prior art, the method provided by the invention comprises the steps of: modeling a phaselocked loop system of the sigma-delta fraction N frequency comprehensive device with jitter noise; and modeling a sigma-delta demodulator. The technical scheme of the invention greatly helps a designer design a circuit, and is convenient for early estimating the influence of the phase noise of the frequency comprehensive device to the whole wireless communication system. The invention can ensure that a circuit designer carries out the rapid simulation to obtain system performances, especially noise performance, thereby avoiding using simulators of SPICE, SpectraRF and the like with very low speed for simulation. The invention can be used for accelerating the design process of the sigma-delta fraction N frequency comprehensive device from top to bottom so as to ensure that the designer accurately predicts the system performances as early as possible, especially indexes of the phase noise and the like.

Description

technical field [0001] The invention belongs to the technical field of wireless propagation communication, and in particular relates to a behavior-level modeling method of a Σ-Δ fractional N frequency synthesizer considering the influence of noise sources. Background technique [0002] A phase-locked loop (PLL: Phase-locked loops) system is widely used in frequency synthesizers (Frequency Synthesizers) of wireless communication products such as mobile phones. At the very beginning, frequency synthesizers were integer N systems, that is, the system output frequency was an integer multiple of the input frequency. In order to improve the accuracy and bandwidth of the frequency synthesizer, a frequency synthesizer with fractional N was invented. Its frequency division multiple can be fractional, so the output frequency can be a fractional multiple of the input frequency. However, because the frequency synthesizer with fractional times divides the frequency in fractional times, ...

Claims

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Application Information

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IPC IPC(8): G06F17/50H03L7/18
Inventor 杨磊
Owner 江苏创通电子股份有限公司
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