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Method for generating vector processing instruction set architecture in high performance computing system

A high-performance computing and instruction processing technology, applied in computing, memory systems, electrical digital data processing, etc., can solve problems such as the inability to further utilize vector data, optimal design, and lack of digital signal processing algorithm analysis and extraction

Active Publication Date: 2010-09-15
BEIJING SMART LOGIC TECH CO LTD
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Problems solved by technology

[0005] Some patents and articles have discussed the instruction set architecture of vector processors, but these instruction sets only discuss the four arithmetic operations of vectors, without analyzing and extracting digital signal processing algorithms, and the obtained instruction set architecture may not be suitable for specifying At the same time, these patents discuss vector computing on the basis of scalar, using scalar computing resources to realize vector computing, and cannot further utilize the inherent parallelism of vector data for optimal design

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  • Method for generating vector processing instruction set architecture in high performance computing system
  • Method for generating vector processing instruction set architecture in high performance computing system
  • Method for generating vector processing instruction set architecture in high performance computing system

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Embodiment Construction

[0073] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0074] Such as figure 1 as shown, figure 1 It is a flow chart of a method for generating a vector processing instruction set structure in a high-performance computing system provided by the present invention, and the method includes the following steps:

[0075] Step 1: Analyze the core algorithms in the field of digital signal processing, and obtain the logical expressions of each core algorithm.

[0076] In this step, first analyze the core algorithms in the current digital signal processing field, summarize the logical expressions of each core algorithm, and understand the computing requirements of the application field from the algorithm level. Core algorithms include at least pulse compression, Doppler processing, ...

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Abstract

The invention discloses a method for generating a vector processing instruction set architecture in a high performance computing system, which comprises the following steps of: 1. analyzing core algorithms in a digital signal processing field to obtain the logical expression of each core algorithm; 2. abstracting element vector operation in the digital signal processing field from the logical expressions; and 3. generating the vector processing instruction set architecture specific to special vector instruction syntax and behaviors based on the abstracted element vector operation. The invention generates the vector processing instruction set applicable to the special field, thereby greatly improving the performance of the processor.

Description

technical field [0001] The invention relates to the technical field of digital signal processing, in particular to a method for generating a vector processing instruction set structure in a high-performance computing system. Background technique [0002] During the past forty years, DSP processors have developed by leaps and bounds. However, DSP computing power must be further improved to meet the current application requirements. Semiconductor technology is the foundation of DSP development and has always been the main driving force for DSP development. In the past, most of the performance improvement of DSP came from the increase of chip operating frequency. However, due to the limitation of integrated circuit manufacturing process and power consumption, the era of increasing the main frequency is over, and the performance of the processor must be further improved by relying on architectural innovation, but the optimization of the architecture can only be aimed at specifi...

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Application Information

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IPC IPC(8): G06F9/45
Inventor 王东琳谢少林尹志刚林啸张志伟闫寒薛晓军
Owner BEIJING SMART LOGIC TECH CO LTD
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