Arithmetic circuit for montgomery multiplication and encryption circuit

一种运算电路、乘法的技术,应用在运算电路领域

Inactive Publication Date: 2010-07-21
SHARP KK
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0030] However, in general, when performing Montgomery multiplication with an arithmetic circuit, for example, when the arithmetic circuit is implemented with an ASIC (Application Specific Integrated Circuit, Application Specific Integrated Circuit), the 2-port RAM is often not supported by the standard ASIC library.
In addition, even when 2-port RAM is supported, only 2-port RAM with a large area by the 2-read 2-write method may be supported

Method used

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  • Arithmetic circuit for montgomery multiplication and encryption circuit
  • Arithmetic circuit for montgomery multiplication and encryption circuit
  • Arithmetic circuit for montgomery multiplication and encryption circuit

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other Embodiment approach

[0074] (1) In the above-mentioned embodiment, the case where the RSA encryption circuit 103 is mounted on the IC card 100 and the encryption process is performed using the circuit 1 of the present invention has been described. In the circuit 103 and the like, decryption processing is performed using the circuit 1 of the present invention.

[0075] (2) In the above embodiment, the case where the circuit 1 of the present invention is used in the RSA encryption circuit 103 has been described, but it can also be used in other encryption circuits or arithmetic circuits using Montgomery multiplication.

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Abstract

An arithmetic circuit capable of Montgomery multiplication using only a one-port RAM is disclosed. In a first read process, b[i] is read from a memory M2 of a sync one-port RAM for storing a[s-1: 0] and b[s-1: 0] and stored in a register R1. In a second read process, a[j] is read from the memory M2, t[j] from a memory M1 of a sync one-port RAM for storing t[s-1: 0], b[i] from the register R1, and a value RC from a register R2, and input to a sum-of-products calculation circuit 10 for calculating t[j]+a[j]*b[j]+RC. In a write process, the calculation result data FH is written in the register R2, and the calculation result data FL in the memory M1 as t[j]. A first subloop process for repeating the second read process, the sum-of-products calculation process and the write process is executed after the first read process.

Description

technical field [0001] The present invention relates to an arithmetic circuit for Montgomery multiplication, and a cipher circuit for performing encryption and decryption by using the arithmetic circuit for Montgomery multiplication. Background technique [0002] In e-commerce transactions using networks such as the Internet for contracts or settlements, for example, there are business transactions (commercial transactions between companies and consumers) conducted by electronic stores that sell goods on the Internet. Consumers can browse the websites of electronic stores, Select an item, specify a payment method and purchase it. [0003] In such an e-commerce transaction, ensuring security against impersonation, eavesdropping, and falsification is an issue. For example, public key cryptography is used as one of authentication techniques for preventing impersonation. Here, public key cryptography is a technology that uses two different keys, an encryption key for encryption...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/72H04L9/30
CPCG06F7/728
Inventor 大山茂郎
Owner SHARP KK
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