Process for encapsulating square flat outer-pin-free encapsulating structure
A technology of packaging structure and packaging technology, which is applied in the manufacture of electrical components, electrical solid devices, semiconductor/solid devices, etc., can solve problems such as process difficulties, burrs and bridging, design restrictions, etc., and achieve simple packaging technology, low cost, and avoid Glitches and the effect of pins bridging each other
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[0024] Hereinafter, the packaging process of the quadflat no-lead package structure according to the embodiment of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the drawings are not to scale and do not precisely reflect the precise structural or performance characteristics of any given embodiment, but are schematic only. In the drawings, the size and relative sizes of layers and regions are exaggerated for clarity.
[0025] Figure 4 It is a schematic diagram showing the structure of the quadrilateral flat no outer lead package according to the present invention. Depend on Figure 4 It can be seen that the quadrilateral flat no-lead package structure according to the present invention comprises: a chip 41; a metal structure 42, on which the chip 41 is loaded at a predetermined position (die pad) on its upper surface; a metal wire 44, which is used to connect the chip The input / output port of 41 and the...
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