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Structure taking part of metal grid as grid medium etching blocking layer with high dielectric constant and integration method

A technology for etching barrier layers and high dielectric constants, which is applied in the manufacture of circuits, electrical components, semiconductors/solid-state devices, etc., can solve problems such as damage to high-K gate dielectric materials, simplify integration complexity, and overcome Fermi The effect of the energy level pinning effect

Inactive Publication Date: 2010-03-17
FUDAN UNIV
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Problems solved by technology

[0005] The object of the present invention is to provide a semiconductor chip integration method to improve the problem of damage to the high-K gate dielectric material when removing the photoresist, overcome the Fermi level pinning effect of the PMOS gate, and simplify the high-K metal gate The complexity of the integration, and provide the structure of the etch barrier layer of the corresponding high-K gate dielectric layer

Method used

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  • Structure taking part of metal grid as grid medium etching blocking layer with high dielectric constant and integration method
  • Structure taking part of metal grid as grid medium etching blocking layer with high dielectric constant and integration method
  • Structure taking part of metal grid as grid medium etching blocking layer with high dielectric constant and integration method

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Embodiment Construction

[0027] Below in conjunction with accompanying drawing and specific embodiment the present invention is described in further detail:

[0028] Step 1: Please refer to figure 1 , provide a silicon substrate 200 that has completed the shallow trench isolation (STI) process, and sequentially form a layer of film 201, a layer of film 202, a layer of film 203, a layer of film 204 and a layer of film 200 on the silicon substrate 200 Film 205. Thin film 201 is SiO 2 , with a thickness in the range of 1 to 5 nm. The thin film 202 and the thin film 203 are high-k dielectric layers, and the thin film 202 is HfSiO. Thin film 203 is Al 2 o 3 , the thin film 204 is TiN or WN, its thickness is in the range of 1 to 10 nanometers, and it is an etching barrier layer. The thin film 205 is a photoresist layer, and the thickness of the photoresist is in the range of 0.3 to 2 microns. After the thin film 202 and the thin film 203 are formed, an annealing treatment is required before the thin...

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Abstract

The invention relates to a structure taking part of a metal grid as a grid medium etching blocking layer with high dielectric constant and an integration method, belonging to the technical field of semiconductor chips. The method comprises the following steps: taking part of the metal grid as the etching blocking layer for etching a high-K material when etching the high-K material; after integrating, enabling the threshold voltage of NMOS and PMOS to conform to requirements by simplified steps. The invention has the advantages of overcoming the nail pricking effect of the fermi energy level ofa PMOS grid, solving the problem that the traditional technique damages a high-K medium when removing photoengraving glue, and simplifying the integration complexity of a high-K metal grid greatly.

Description

technical field [0001] The invention belongs to the technical field of semiconductor chips, and in particular relates to a structure and an integration method of a high dielectric constant (high K) gate dielectric and a metal gate. Background technique [0002] In recent years, microelectronics technology with silicon integrated circuits as the core has developed rapidly. The development of integrated circuit chips basically follows Moore's law, that is, the integration level of semiconductor chips doubles every 18 months. However, as the integration of semiconductor chips continues to increase, the channel length of MOS transistors is also continuously shortened. When the channel length of MOS transistors becomes very short, the short channel effect will degrade the performance of the semiconductor chip, or even fail to operate normally. Work. [0003] In order to overcome the adverse effects caused by short channel effects (such as threshold voltage drop, etc.), MOS trans...

Claims

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Application Information

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IPC IPC(8): H01L21/822H01L21/8238H01L21/28H01L21/336
Inventor 王鹏飞孙清清丁士进张卫
Owner FUDAN UNIV
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