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Multi-core onboard spacecraft computer based on FPGA

A spaceborne computer, multi-core technology, applied in the field of aerospace data processing, can solve the problem of slow processing speed of spaceborne computer, achieve the effect of retaining flexibility, improving performance, and improving performance

Inactive Publication Date: 2009-07-29
HARBIN INST OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The purpose of the present invention is to solve the problem that the processing speed of the on-board computer that adopts the ASIC software implementation mode is slow, and a multi-core on-board computer based on FPGA is provided

Method used

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  • Multi-core onboard spacecraft computer based on FPGA

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specific Embodiment approach 1

[0007] Specific embodiment one: below in conjunction with Fig. 1 illustrate present embodiment, present embodiment comprises FPGA1 based on SRAM, n PROM2, n SRAM3, antifuse FPGA4 and configuration NOR type flash memory 5,

[0008] The FPGA1 based on SRAM comprises n processors, which are respectively the first processor 1-1, the second processor 1-2 ... the nth processor 1-n, and the input end of each processor is connected to the input terminal of a PROM2. The output terminals are connected, and the cache input and output terminals of each processor are connected to the input and output terminals of a SRAM3.

[0009] The antifuse FPGA4 includes a read-back brush interface circuit 4-1, a monitoring circuit 4-2 and a control circuit 4-3, and the configuration file input and output terminals of the read-back brush interface circuit 4-1 and the configuration file of FPGA1 based on SRAM The input and output terminals are connected, the heartbeat signal output terminal of the first...

specific Embodiment approach 2

[0016] Embodiment 2: The difference between this embodiment and Embodiment 1 is that the heartbeat signal is a pulse signal output by the I / O port of the processor, and other components and connection methods are the same as Embodiment 1.

[0017] The normal output pulse signal is a waveform with high and low level changes according to a certain period, similar to a heartbeat signal; abnormality means that the output pulse signal is always high, often low or has an irregular cycle.

specific Embodiment approach 3

[0018] Specific embodiment three: the difference between this embodiment and embodiment one is that it also includes a backup NOR flash memory 6, the input and output terminals of the backup NOR flash memory 6 are connected with the data input and output terminals of FPGA1 based on SRAM, and other components And the connection method is the same as the first embodiment.

[0019] Since the SRAM-based FPGA1 has power-off data volatility, it brings the problem of information loss to the on-board computer system. In order to solve this problem, the SRAM-based FPGA1 needs to be reconfigured before it is reconfigured with new functional modules. Through a certain memory access instruction, the data to be protected in the SRAM-based FPGA1 is read into the backup NOR flash memory 6, and when the SRAM-based FPGA1 is powered on again, the SRAM-based FPGA1 is read back from the backup NOR flash memory 6 The data is protected, which greatly improves the security of the on-board computer s...

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Abstract

The invention relates to a multi-core satellite-bone computer, belonging to the data processing technical field of aerospace and aiming at solving the problem of slow processing speed of the satellite-bone computer by adopting an ASIC software realization mode. The satellite-bone computer comprises an FPGA based on an SRAM, n PROMS, n SRAMS, an anti-fuse FPGA and a configuration NOR type flash memory, wherein the FPGA based on the SRAM forms a multi-core structure with n processors, the anti-fuse FPGA comprises a read-back brush write interface circuit, a monitoring circuit and a control circuit, the monitoring circuit monitors the health state of the n processors, if an abnormal part needs reconstruction, the read-back brush write interface circuit reads the configuration file of the FPGA based on the SRAM at set speed, compares the configuration file of the FPGA with an original configuration file, and reconstructs the error parts if different. The multi-core satellite-bone computer can realize automatic switching system function by FPGA hardware programming according to satellite missions.

Description

technical field [0001] The present invention relates to a multi-core on-board computer and its implementation method, which can independently change the system function according to the mission of the satellite, and perform partial reconfiguration and other fault handling through hardware programming, especially related to the data processing of the aerospace industry. technology field. Background technique [0002] With the continuous development of electronic technology and computer technology, the miniaturization design of spacecraft electronic systems has attracted more and more attention, and the high-density functional integration has also put forward higher requirements for the performance of on-board electronic systems. Traditional onboard computers use ASICs to divide system functions and tasks through the design of operating system software. At the same time, the various tasks of the operating system complete the calling of system functions through a certain synchr...

Claims

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Application Information

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IPC IPC(8): G06F15/80
Inventor 孙兆伟刘源兰盛昌张锦绣叶东赵丹范国臣王松林杰徐国栋
Owner HARBIN INST OF TECH
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