Method for manufacturing mask ROM

Abstract

The invention discloses a mask-ROM manufacturing method; wherein, the method makes use of a gate material layer without doping to structure a gate, so that the process flow is compatible to the standard CMOS process and the problem of logic process non-compatibility caused by a pre-doped gate material layer is avoided. At the same time, an ON-NO two-step sidewall method is used, that is, after a bottom silicon oxide layer and a first silicon nitride layer are formed, a gate array dielectric layer of a storage unit region is inserted to fill the process, so as to form a second silicon nitride layer and a top silicon oxide layer. Therefore, a relatively thin ON layer is initially formed to expand the deposited process space of the dielectric layer, so that the integration of the semiconductor memory can be further enhanced; in the follow-up etching, under the protection of the second silicon nitride layer, the loss of the dielectric layer between the gate arrays can be reduced; moreover, the doped ion penetration can be effectively inhibited in the gate doping process, and the probability of leakage current among the storage units can also be reduced.

Description

technical field [0001] The invention relates to a manufacturing method of a semiconductor device, in particular to a manufacturing method of a mask read-only memory (MROM). Background technique [0002] Mask read-only memory (MROM) is one of the common types of semiconductor memory, which is widely used in electronic products such as computers. The mask read-only memory is composed of a memory cell array and a peripheral logic circuit. The memory cell array is usually composed of mutually orthogonal bit lines and word lines: the embedded layer is formed in the memory cell area by ion implantation technology, and the bit line can be formed by further heat treatment. Lines, and word lines are usually gate arrays, which are formed by photolithography and etching processes. The peripheral logic circuit often includes a plurality of logic transistors. In order to simplify the manufacturing process, the gates of the logic transistors of the peripheral logic circuit and the gate a...

AI Technical Summary

Problems solved by technology

However, in the standard CMOS process, the gate doping types of PMOS and NMOS are different, so that the existing mask read-only memory manufacturing process is not compatible with the standard CMOS logic process technology, and in the subsequent doping implantation, resulting in interference with memory performance

[0004] In addition, in the existing mask ROM manufacturing process, tungsten is often deposited on the gate to reduce the resistance of the gate structure

However, the formation process of the gate structure is the front-end process of semiconductor manufacturing, which has high requirements on the cleanliness of the environment, and often does not want to involve dirty processes such as tungsten, because this will lead to the mixed use of front-end and back-end machines and increase the complexity of the process Spend

[0005] In addition, the resistance of the active area of ​​the peripheral logic circuit is large, which will cause the speed of some logic transistors to be difficult to meet the requirements. Therefore, it is necessary to form metal silicide on the active area of ​​these transistors to solve this problem.

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