Capacitive coupling-type transmitting and receiving circuits for information signal
一种静电耦合、信号收发的技术,应用在使用电容耦合的近场传输系统、静态指示器、阴极射线管指示器等方向,能够解决难实用化等问题,达到防止输入容限降低、低功耗化的效果
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Embodiment 1
[0031] figure 1 It is a schematic configuration diagram for explaining the display device of the first embodiment of the present invention. The display device is equipped with an electrostatic coupling type signal transceiver circuit according to the present invention. figure 1 (a) shows the display panel substrate 200, figure 1 (b) shows the transmission board 100. In the display panel substrate 200, the display portion 10 is formed or mounted on an insulating substrate 201, which is preferably glass. Here, the display unit 10 means a liquid crystal display device or the like. Furthermore, on the insulating substrate 201, a reception signal processing circuit 11, a plurality of reception electrostatic electrodes 14 and 15, and an impedance conversion circuit 16 connected to each reception electrostatic electrode 14 are formed. The receiving electrostatic electrode 15 is used to maintain a common potential with respect to the other receiving electrostatic electrodes, and no im...
Embodiment 2
[0054] Picture 9 It is a schematic configuration diagram for explaining the display device of the second embodiment of the present invention. Show with figure 1 Similarly, the structure of a transmission substrate that transmits display signals via a non-contact transmission path and a display panel that realizes reception. Right and figure 1 The same functional parts are marked with the same symbols. In Picture 9 In this case, it is assumed that transmission is performed by assigning two sensing electrodes for each signal to be transmitted (balanced transmission).
[0055] The operation in the transmission board 100 is substantially the same as in the first embodiment. In the case of balanced transmission, the transmission line 2 is composed of a pair (two) of transmission lines to form a signal line and its reverse signal line, and its structure is completely symmetrical with respect to the transmission direction. In addition, when the distance between the signal processing...
Embodiment 3
[0058] Picture 11 It is used to explain another configuration example and operation waveform diagram of the pulse logic-level logic conversion circuit provided on the display panel substrate of the third embodiment of the present invention. Picture 11 (a) is another example of the pulse logic-level logic conversion circuit on the display panel substrate 200 side. As mentioned above, the example shown in Example 1 Figure 8 The conversion circuit of (a) has timing restrictions on data input. and Picture 11 The circuit shown can detect the rising edge of data input independently of the logic state of the clock signal CL.
[0059] The conversion circuit 16 is mainly composed of three D-flip-flops 331, 332, and 34. Combine Picture 11 The voltage waveform diagrams shown in (b) illustrate the operation of the circuit. The data signal DATA and the clock signal CL sensed on the side of the display panel substrate 200 are converted into binary digital signals by a buffer (an impedanc...
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