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On site programmable gate array single particle effect test method

A technology of single event effect and testing method, which is applied in the direction of electronic circuit testing, non-contact circuit testing, etc., can solve the problem that the testing method is in the groping stage, and achieve the effect of accurate and reliable test results and exclusion of external interference

Inactive Publication Date: 2009-06-17
CHENGDU SINO MICROELECTRONICS TECH CO LTD
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  • Application Information

AI Technical Summary

Problems solved by technology

SRAM-based Field Programmable Gate Array (FPGA), as a CMOS VLSI with SRAM, its test method is still in the exploration stage

Method used

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  • On site programmable gate array single particle effect test method
  • On site programmable gate array single particle effect test method

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0018] see figure 1 . The invention provides a field programmable gate array (FPGA) based SRAM single event effect ground simulation test method. Including the construction of the experimental system and the test circuit board and software method used. Power up the circuit board where the device under test is located, bombard it with protons and heavy particles from the heavy particle accelerator and proton accelerator, use an ammeter outside the shielded room to monitor the current change, monitor whether the function is still there through the camera, and connect it with the parallel port of the computer Test the JTAG interface of the board, use the EDA tool provided by the FPGA manufacturer to read back the value of the FPGA internal SRAM and save it as a file, and then use ULTRAEDIT to compare the data saved at each time with the initial data, and observe at what time, whether there is SRAM Flip.

[0019] Experimental environment such as figure 1 shown, including the f...

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PUM

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Abstract

The invention provides a test method for field programmable gate array single particle effect, relating to an integrated circuit technology. The invention comprises the following steps: 1) the package of FPGA is removed, and FPGA is arranged on a test circuit board; 2) FPGA is configured, and then SRAM data are read back and recorded; 3) the test circuit board is arranged in a test room and a particle source emits single particles to bombard FPGA; 4) SRAM data are read back and recorded; 5) data of steps 2) and 4) are compared, and reversed digits of SRAM are determined; 6) when the reversal times reach a preset value or after the period of time without reversal reaches a preset time value, the particle source is changed, FPGA is electrified again, the FPGA is confirmed to return to the initial state, and then steps 3) and 5) are repeated; 7) the data are processed: the reversal section of the LET value is calculated and a reversal curve is generated. The method can precisely test the impact of the single particle effect and eliminate external interferences, thus ensuring the correction and reliability of the test results.

Description

technical field [0001] The invention relates to integrated circuit testing technology. Background technique [0002] As spacecraft fly in space, they are always in a radiation environment composed of charged particles. High-energy protons and heavy ions in the space radiation environment can cause single event effects in semiconductor devices in spacecraft electronic systems. At the same time, experiments have shown that neutrons in the atmospheric environment can also cause single event effects in avionics. Especially devices with SRAM units (such as SRAM memory, FPGA, etc.), are more sensitive to single event effects. Single event effects occur during aerospace operations, but a large number of research experiments are carried out on the ground, especially the evaluation of the anti-single event effect ability of the components required for spacecraft is based on the results of ground simulation tests. The accuracy, reliability and credibility of the test data are direc...

Claims

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Application Information

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IPC IPC(8): G01R31/303
Inventor 李威黄国辉杨志明孙振维郑博文
Owner CHENGDU SINO MICROELECTRONICS TECH CO LTD
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