Test construction for transistor

Abstract

The invention provides a test structure for transistors. The structure comprises an electric-charge storage element and a discharge element which are in parallel connection between a grid of a tested transistor and a substrate, wherein the area of the electric-charge storage element is larger than that of the transistor. The electric-charge storage element and the discharge element are taken as protective elements, can prevent instantaneous high current produced by electrostatic discharge from destroying a thin-grid oxide layer of a semiconductor transistor and even breaking down a grid of the semiconductor transistor so as to cause permanent damage.

Description

technical field [0001] The invention relates to a test structure of a transistor. Background technique [0002] Complementary metal-oxide-semiconductor (CMOS) process technology uses thin film deposition technology (Thin Film Deposition) to layer-deposit conductors, semiconductors, and insulating layers on the surface of the wafer to be manufactured to form semiconductor devices such as transistors or capacitors. . [0003] During the wafer manufacturing process, wafer-level reliability testing (WLR, Wafer Level Reliability) or package-level reliability testing (PLR, Package Level Reliability) is performed on test samples (samples) of semiconductor devices to monitor the manufacturing process in real time. The introduced defects are very necessary. The reliability test will feed back the test results to the production line in time, so as to strengthen the control of the relevant process steps, so as to obtain high-quality and high-reliability products. [0004] However, be...

AI Technical Summary

Problems solved by technology

figure 1 The drain current Idn1, gate current Ign1, substrate current Ibn1, figure 2 The drain current Idp1, gate current Igp1, and substrate current Ibp1 of the multiple PMOS transistors shown fluctuate, especially the fluctuations of the gate currents Ign1, Igp1, substrate currents Ibn1, and Ibp1 are very large, that is, ESD destroys the thin gate oxide layer of MOS transistors and causes the gate current and substrate current of multiple MOS transistors to deviate from the standard value range.

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