Buffer cell circuit for resisting single-particle transient state
A single-event transient and anti-single event technology, which is applied in the direction of logic circuit connection/interface layout, logic circuit coupling/interface using field effect transistors, etc., can solve the problems of high overhead of area and power consumption, and achieve area and power The effect of small loss, effective suppression of single-event transient pulse ability, and fast speed
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[0015] The present invention will be further described below in conjunction with the accompanying drawings.
[0016] Such as figure 1 , figure 2 As shown, the anti-single event transient buffer unit circuit of the present invention is composed of a single event transient suppression buffer circuit 811 and a signal delay circuit 812 .
[0017] The signal delay circuit is composed of an inverter and a delay unit, which can generate a signal AN that is inverse to the input signal A, a delayed signal A~ that is in phase with the input signal A, and a delayed signal AN~ that is inverse to the input signal A. The length of the signal delay time TD depends on the function of the delay unit in the delay circuit. The delay generated by the inverter is much smaller than the delay of the delay unit, so its influence on the signal delay is ignored.
[0018] The present invention provides two single event transient suppression buffer circuits. One is an N-type single event transient su...
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