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OPC correcting method for forming auxiliary through hole

A polygonal and metal wire technology, applied in the field of OPC correction for forming auxiliary through holes, can solve the problems such as the drop of qualified rate, danger, open circuit, etc., so as to reduce the possibility of open circuit, improve the process tolerance, and reduce the number of effects.

Inactive Publication Date: 2011-05-11
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This approach can be very dangerous when process tolerances are small, such as blind vias due to photoresist fragments or defects falling into vias
Especially for those vias that are relatively isolated, open circuits are often generated, resulting in a decline in the final yield

Method used

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  • OPC correcting method for forming auxiliary through hole
  • OPC correcting method for forming auxiliary through hole
  • OPC correcting method for forming auxiliary through hole

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0081] FIGS. 1A to 1G are diagrams showing the first embodiment of the present invention, taking a logic product of 0.15 μm as an example to explain the process of setting auxiliary via holes.

[0082] As shown in FIG. 1A, there is a first through hole 31 between the first metal line 11 of the first layer and the fourth metal line 24 of the second layer, and a first through hole 31 is formed between the second metal line 12 of the first layer and the third metal line of the second layer. There is a second through hole 32 between them, there is a third through hole 33 between the third metal line in the first layer and the second metal line in the second layer, and there is a fifth metal line in the first layer and the fifth metal line in the second layer. There is a fourth through hole 34 between them, and a through hole 35 is between the fourth metal line of the first layer and the sixth metal line of the second layer.

[0083] As shown in FIG. 1B , firstly, each via is check...

Embodiment 2

[0091] 2A to 2H are schematic diagrams showing the second embodiment of the present invention, taking a logic product of 0.18 μm as an example to illustrate the formation process of auxiliary via holes.

[0092] As shown in FIG. 2A, there is a first through hole 31 between the first metal line 11 of the first layer and the first metal line of the second layer, and between the second metal line 12 of the first layer and the second metal line of the second layer. There are a second through hole 32 , a third through hole 33 and a fourth through hole 34 therebetween.

[0093] Generally, a through hole whose distance from any other surrounding through holes is larger than Lmin is regarded as an isolated through hole. Among the above through holes, the through hole 31 is an isolated through hole, as shown in FIG. 2B .

[0094] As shown in FIG. 2C , four auxiliary through holes are set at the minimum design interval (Min-Design-Pitch) around the isolated through hole 31 from the orig...

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Abstract

An OPC correction method for forming an auxiliary through hole is as follows: other through holes and metal wires are searched in a certain range nearby isolated through holes between two layers of metal wires; auxiliary through holes are formed nearby the isolated through holes; the through holes and the metal wires are not existed in the certain range of the isolated through holes; the auxiliary through holes extend a size added value towards periphery, and then extend towards the direction of original through holes to be connected with the original through holes and overlap with the under layer metal wire; and finally the conventional OPC correction is carried out on the improved metal wire and the layout of the through holes.

Description

technical field [0001] The invention relates to an OPC (Optical Proximity Correction) correction method for integrated circuit layout on a mask used in semiconductor manufacturing, in particular to an OPC correction method for forming auxiliary through holes for isolated through holes between two layers of metal lines. Background technique [0002] In the back-end manufacturing process of semiconductors, in order to form metal interconnection lines, it is necessary to form via holes between two adjacent layers of metal lines to realize metal interconnection. As circuit density increases and critical dimensions become smaller and smaller, the size of wires and wire spacing and through holes becomes smaller and denser, even reaching sub-micron. When the integrated circuit pattern on the mask is transferred to the photoresist layer on the wafer through exposure, deformation often occurs due to the optical proximity effect, and the through holes of the same size in the pattern s...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G03F1/14G03F1/36
Inventor 洪齐元
Owner SEMICON MFG INT (SHANGHAI) CORP
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