Multi-stage test response compactors

A compressor and tested technology, applied in the direction of electronic circuit testing, instrumentation, measuring electronics, etc., to achieve high diagnostic resolution and reduced test time

Inactive Publication Date: 2009-04-08
MENTOR GRAPHICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Test response compressors exist, but the compression ratio of these devices is usually limited to the ratio of the number of scan chains to the number of compressor outputs

Method used

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Examples

Experimental program
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Embodiment approach 100

[0066] 1 shows an exemplary implementation 100 of a compressor architecture (X-Press compressor architecture) in an embedded deterministic test environment with n scan chains 120, which includes a first test response compressor 110 and a second test Response compressor 152 . A compressed test stimulus may be provided to scan chain 120 via decompressor 130 via one or more input channels (or input paths) 132 , 134 . In some embodiments, these channels may also be used in conjunction with input channels 136 , 138 to deliver mask bits (mask instructions) to selector circuit 140 via components 160 , 162 . In certain implementations, the components 160, 162 are pipeline registers, while in other implementations they may be demultiplexers. In other embodiments, there may not necessarily be a data dependency between the compressed test stimulus and the mask bits, as discussed more fully below. Compressor 110 may be a spatial compressor (or spatial compressor) including an XOR or XNO...

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Abstract

Disclosed herein are exemplary embodiments of a so-called 'X-press' test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 100Ox. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.

Description

[0001] Cross References to Related Applications [0002] This application claims priority to: U.S. Provisional Patent Application No. 60 / 774,431, filed February 17, 2006, entitled "Multi-Stage Test Response Compactors"; -Stage Test Response Compactors," U.S. Provisional Patent Application No. 60 / 832,466; and U.S. Provisional Patent Application No. 60 / 853,055, filed October 20, 2006, entitled "Multi-Stage Test Response Compactors." Each of the aforementioned applications is hereby incorporated by reference. technical field [0003] The disclosed technology relates to testing electronic circuits, particularly testing electronic circuits using compression hardware. Background technique [0004] Testing electronic circuits for possible defects can generate large amounts of test data (eg, test responses), especially if the circuits are large and / or complex. Test responses stored by scan chains in the circuit may be compressed to allow analysis of the response using fewer test ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/28
CPCG01R31/318563G01R31/318547G01R31/318566G01R31/3177G01R31/2851G01R31/31723G01R31/31727
Inventor G·姆鲁加尔斯基J·拉斯基J·特伊泽W-T·程N·玛克赫吉M·卡萨布
Owner MENTOR GRAPHICS CORP
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