On site programmable gate array on-chip programmable system based on DW8051 core

Abstract

The invention provides a programmable system on a field programmable gate array chip based on a DW8051 core, the programmable system on the chip takes the DW8051 core as a core, comprising a memory, an external interface circuit and a clock reset circuit to provide a clock and a reset signal to the whole system; the memory comprises three memory spaces of a ROM program memory, an expanding data memory and an internal data memory; the external interface circuit comprises three small modules of an SFR decoding module, an IIC bus interface and an external small system; the clock reset circuit comprises two modules of a clock signal generation module and a reset generation module. The programmable system on the chip of the invention improves the operation speed of the control system due to the integration of the DW8051 core at the interior; as the FPGA realizes the internal control logic, thus enhancing the anti-interference and the stability of the system. The programmable system can modify the corresponding logic algorithm according to the actual needs of the system, thus having great flexibility and configurability.

Description

technical field [0001] The present invention relates to a programmable system on chip (SOPC) based on FPGA (Field Programmable Gate Array). Background technique [0002] Traditionally, to design an embedded system, designers need to choose from three different categories of hardware devices—processors, logic devices, and memory. Today, combining all of these devices creates a single SOC (system-on-chip) solution, increasing speed, reducing size, and more importantly, reducing overall system cost. Developing new SOC devices requires many key factors, including new development tools, leading manufacturing technologies and semiconductor IP cores. Considering the technological development, the ASIC (Application Specific Integrated Circuit) based SOC industry still faces many challenges, thus hindering its development. Using CPLD (Complex Programmable Logic Device) can make SOC design have remarkable flexibility, but because the processor core is usually a hard core, its scalab...

AI Technical Summary

Problems solved by technology

Due to uneven technology, some on-chip programmable systems currently on the market run at low speed, and the system's anti-interference and stability are poor

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