Method for enhancing pattern uniformity

Abstract

The invention relates to a method for enhancing pattern uniformity, suitable for a substrate comprising a pattern concentration region and a pattern quasi-vacant region. The substrate is sequentiallyformed with a barrier layer and a bottom antireflective layer. The method comprises: first forming a patterned photo-resistant layer; the patterned photo-resistant layer comprises a first photo-resistant pattern in the pattern concentration region, and a second photo-resistant pattern in the pattern quasi-vacant region, wherein the size of the second photo-resistant pattern is larger than the sizeof the first photo-resistant pattern; then carrying the first clipping step to realize micro-patterned process on the photo-resistant layer, meanwhile, removing part of the bottom antireflective layer by using the patterned photo-resistant layer as a covering shield; then carrying out the second clipping step to realize micro-pattern process on the photo-resistant layer and the bottom antireflective layer simultaneously, and minimizing the size differences between the second photo-resistant pattern and the first photo-resistant pattern. The invention can be used for enhancing the pattern uniformity.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor structure, in particular to a method for improving pattern uniformity. Background technique [0002] With the rapid development of the field of integrated circuits, high performance, high integration, low cost, light weight and small size have become the goals pursued by the design and manufacture of electronic products. For the current semiconductor industry, in order to meet the above goals, it is often necessary to manufacture components with multiple functions on the same chip, for example, combining read-only memory, static random access memory, flash memory or dynamic random access memory. Access memory, logic circuits, digital circuits, etc. are fabricated on the same chip, which is the so-called System On Chip (SOC). [0003] However, the traditional system-on-chip (SOC) integrates various components on the same chip, which can improve its functionality and electrical function...

AI Technical Summary

Problems solved by technology

However, this method only shrinks the patterned photoresist layer on the memory cell area and the semi-open area of ​​the pattern, but the difference in the size of the pattern on the memory cell area and the semi-open area of ​​the pattern is still unresolved.

As a result of poor pattern uniformity, the conductive wires formed on the semi-empty area of ​​the pattern will still be larger than the conductive wires on the memory cell area, which cannot meet the electrical requirements of the device, and reduce the operating efficiency and electrical performance of the device.

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