Programmable logic device fast logical block mapping method

Abstract

The invention relates to a rapid logic mapping method for FPGA, belonging to the electronic technique field. A demixing and classification mapping to a programmable logic unit is raised to reduce the complexity of algorithm, a match degree coefficient is introduced to enhance the performance of the algorithm, and then a high performance rapid logic mapping method for FPGA is obtained. Experimental data show that the performance of the invention is enhanced by 12.59 percent compared to the conventional figure matching with the structure mapping algorithm, the complexity of algorithm is decreased largely from O(m) down to O(m), the invention can be widely applied in logic unit structure mapping for artery FPGA in modern times, the extendibility of FPGA logic unit mapping module in the operating efficiency and algorithm of the entire FPGA CAD flow is enhanced largely. The high performance rapid FPGA logic unit mapping method can also conduct the design of the FPGA programmable logic unit hardware structure, so that the structure advantages and disadvantages of the programmable logic unit can be estimated by the hardware design engineer before making chips, the design period is shortened largely, the success rate of a new device is increased, the design cost is saved.

Description

technical field [0001] The invention belongs to the field of electronic technology (Electronic Design Automation, EDA), and in particular relates to a software design and implementation method of a programmable logic device (FPGA) structure. technical background [0002] FPGA design includes its chip structure design and supporting software system design. Among them, the software system design must match the chip hardware structure. An efficient CAD system is a necessary condition for using FPGA. In traditional FPGA design, different hardware structures are often paired with different software algorithms: For example, the dedicated mapping algorithm lut2xc3k is used to process the programmable logic block PLB (Programming Logic Block) of XILINX XC3000 FPGA, and the dedicated mapping algorithm lut2xc4k is used to process XILINX XC4000 FPGA programmable logic unit, these two special algorithms are integrated in a system called RASP (Rapid System Prototyping) 【1】 . The direc...

AI Technical Summary

Problems solved by technology

But the problem is that with the increase of the types of basic functional elements of the logic unit, the complexity of the algorithm increases exponentially, which is unacceptable in terms of running time

In addition, the performance of this algorithm cannot be compared with that of dedicated mapping algorithms.

Images