Soldering pad structure in semiconductor apparatus and related method

Abstract

The invention discloses a welding pad structure which is arranged in a semiconductor device, and a method which is used for forming the welding pad structure. The semiconductor device comprises a base, and the welding pad structure comprises a connecting structure and an inductance structure. The connecting structure allows a lead wire to be connected on. The inductance structure is coupled with the connecting structure, and is used for reducing the equivalent capacitance value between the lead wire and the base.

Description

technical field [0001] The invention relates to a welding pad in a semiconductor device, in particular to a welding pad structure which can reduce the equivalent capacitance value between a lead and a substrate. Background technique [0002] Chips are one of the most common components in various electronic devices today. Generally speaking, a solid bonding pad must be provided on the chip, so that external leads (Bonding wire) can be electrically connected to the core circuit of the chip through the bonding pad. Through the bonding pads, the core circuit in the chip can transmit output signals to external circuits, or receive input signals transmitted from external circuits. In the known semiconductor process, in order to avoid the occurrence of the peel-off effect and ensure the reliability of the pad, multiple metal layers are generally used as the main structure of the pad. [0003] However, for the known pad structure, parasitic capacitance exists between every two adj...

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Problems solved by technology

In addition, the equivalent capacitance of the pad will also reduce the noise immunity (Noise immunity) of the pad to the substrate, resulting in an increase in the noise figure (Noise figure)

These negative effects will reduce the overall performance of the chip, especially for chips with high-speed application circuits, the reduction in chip performance will be more obvious

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